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M68HC08及HCS08系列单片机bootloader引导程序源码/示例

TPM1C2VH:   equ   $3C         ;TPM1 channel 2 value register (high)
TPM1C2VL:   equ   $3D         ;TPM1 channel 2 value register (low)

TPM2C2VH:   equ   $6C         ;TPM2 channel 1 value register (high)
TPM2C2VL:   equ   $6D         ;TPM2 channel 1 value register (low)

TPM2C3SC:   equ   $6E         ;TPM2 channel 3 status and control
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH3F:       equ   7           ;(bit #7) channel 3 flag
CH3IE:      equ   6           ;(bit #6) ch 3 interrupt enable
MS3B:       equ   5           ;(bit #5) mode select B
MS3A:       equ   4           ;(bit #4) mode select A
ELS3B:      equ   3           ;(bit #3) edge/level select B
ELS3A:      equ   2           ;(bit #2) edge/level select A
; bit position masks
mCH3F:      equ   %10000000   ;channel 3 flag
mCH3IE:     equ   %01000000   ;ch 3 interrupt enable
mMS3B:      equ   %00100000   ;mode select B
mMS3A:      equ   %00010000   ;mode select A
mELS3B:     equ   %00001000   ;edge/level select B
mELS3A:     equ   %00000100   ;edge/level select A

TPM2C3VH:   equ   $6F         ;TPM2 channel 1 value register (high)
TPM2C3VL:   equ   $70         ;TPM2 channel 1 value register (low)

TPM2C4SC:   equ   $71         ;TPM2 channel 4 status and control
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH4F:       equ   7           ;(bit #7) channel 4 flag
CH4IE:      equ   6           ;(bit #6) ch 4 interrupt enable
MS4B:       equ   5           ;(bit #5) mode select B
MS4A:       equ   4           ;(bit #4) mode select A
ELS4B:      equ   3           ;(bit #3) edge/level select B
ELS4A:      equ   2           ;(bit #2) edge/level select A
; bit position masks
mCH4F:      equ   %10000000   ;channel 4 flag
mCH4IE:     equ   %01000000   ;ch 4 interrupt enable
mMS4B:      equ   %00100000   ;mode select B
mMS4A:      equ   %00010000   ;mode select A
mELS4B:     equ   %00001000   ;edge/level select B
mELS4A:     equ   %00000100   ;edge/level select A

TPM2C4VH:   equ   $72         ;TPM2 channel 1 value register (high)
TPM2C4VL:   equ   $73         ;TPM2 channel 1 value register (low)

****  Internal Clock Generator Module (ICG)  ************************************************
;*
ICGC1:      equ   $48         ;ICG control register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
RANGE:      equ   6           ;(bit #6) frequency range select
REFS:       equ   5           ;(bit #5) reference select
CLKS1:      equ   4           ;(bit #4) clock select bit 1
CLKS0:      equ   3           ;(bit #3) clock select bit 0
OSCSTEN:    equ   2           ;(bit #2) oscillator runs in stop
; bit position masks
mRANGE:     equ   %01000000   ;frequency range select
mREFS:      equ   %00100000   ;reference select
mCLKS1:     equ   %00010000   ;clock mode select (bit-1)
mCLKS0:     equ   %00001000   ;clock mode select (bit 0)
mOSCSTEN:   equ   %00000100   ;enable oscillator in stop mode

ICGC2:      equ   $49         ;ICG control register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
LOLRE:      equ   7           ;(bit #7) loss of lock reset enable
MFD2:       equ   6           ;(bit #6) multiplication factor div
MFD1:       equ   5           ;(bit #5)  "
MFD0:       equ   4           ;(bit #4)  "
LOCRE:      equ   3           ;(bit #3) loss of clock reset enable
RFD2:       equ   2           ;(bit #2) reference divider
RFD1:       equ   1           ;(bit #1)  "
RFD0:       equ   0           ;(bit #0)  "
; bit position masks
mLOLRE:     equ   %10000000   ;loss of lock reset enable
mMFD2:      equ   %01000000   ;multiplication factor divider
mMFD1:      equ   %00100000   ; "
mMFD0:      equ   %00010000   ; "
mLOCRE:     equ   %00001000   ;loss of clock reset enable
mRFD2:      equ   %00000100   ;reference divider bits
mRFD1:      equ   %00000010   ; "
mRFD0:      equ   %00000001   ; "

ICGS1:      equ   $4A         ;ICG status register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CLKST1:     equ   7           ;(bit #7) clock mode status 1
CLKST0:     equ   6           ;(bit #6) clock mode status 0
REFST:      equ   5           ;(bit #5) reference clock status
LOLS:       equ   4           ;(bit #4) loss of lock status
LOCK:       equ   3           ;(bit #3) FLL lock status
LOCS:       equ   2           ;(bit #2) loss of clock status
ERCS:       equ   1           ;(bit #1) ext ref clk status
ICGIF:      equ   0           ;(bit #0) ICG interrupt flag
; bit position masks
mCLKST1:    equ   %10000000   ;clock mode status 1
mCLKST0:    equ   %01000000   ;clock mode status 0
mREFST:     equ   %00100000   ;reference clock status
mLOLS:      equ   %00010000   ;loss of lock status
mLOCK:      equ   %00001000   ;FLL lock status
mLOCS:      equ   %00000100   ;loss of clock status
mERCS:      equ   %00000010   ;ext ref clk status
mICGIF:     equ   %00000001   ;ICG interrupt flag

ICGS2:      equ   $4B         ;ICG status register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
DCOS:       equ   0           ;(bit #0) DCO Clock Stable
; bit position masks
mDCOS:      equ   %00000001   ;DCO Clock Stable

ICGFLTU:    equ   $4C         ;ICG filter register (upper 4 bits in bits 3:0)
ICGFLTL:    equ   $4D         ;ICG filter register (lower 8 bits)

ICGTRM:     equ   $4E         ;ICG trim register

;****  System Integration Module (SIM)  *****************************************************
;*
SRS:        equ   $1800       ;SIM reset status register
; bit position masks
mPOR:       equ   %10000000   ;power-on reset
mPIN:       equ   %01000000   ;external reset pin
mCOP:       equ   %00100000   ;COP watchdog timed out
mILOP:      equ   %00010000   ;illegal opcode
mICG:       equ   %00000100   ;illegal address access
mLVD:       equ   %00000010   ;low-voltage detect

SBDFR:      equ   $1801       ;system BDM reset register
; bit position masks
mBDFR:      equ   %00000001   ;BDM force reset

SOPT:       equ   $1802       ;SIM options register (write once)
; bit position masks
mCOPE:      equ   %10000000   ;COP watchdog enable
mCOPT:      equ   %01000000   ;COP time-out select
mSTOPE:     equ   %00100000   ;stop enable
mBKGDPE:    equ   %00000010   ;BDM pin enable

SDIDH:      equ   $1806       ;system device identification 1 register (read-only)
SDIDL:      equ   $1807       ;rev3,2,1,0 + 12-bit ID. GB60 ID = $002
; bit position masks within SDIDH
mREV3:      equ   %10000000   ;device revision identification (high)
mREV2:      equ   %01000000   ;device revision identification
mREV1:      equ   %00100000   ;device revision identification
mREV0:      equ   %00010000   ;device revision identification (low)

;****  Power Management and Control Module (PMC)  *******************************************
;*
SRTISC:     equ   $1808       ;System RTI ststus and control register
; bit position masks
mRTIF:      equ   %10000000   ;real-time interrupt flag
mRTIACK:    equ   %01000000   ;real-time interrupt acknowledge
mRTICLKS:   equ   %00100000   ;real-time interrupt clock select
mRTIE:      equ   %00010000   ;real-time interrupt enable
mRTIS2:     equ   %00000100   ;real-time interrupt delay select (high)
mRTIS1:     equ   %00000010   ;real-time interrupt delay select
mRTIS0:     equ   %00000001   ;real-time interrupt delay select (low)


SPMSC1:     equ   $1809       ;System power management status and control 1 register
; bit position masks
mLVDF:      equ   %10000000   ;low voltage detect flag
mLVDACK:    equ   %01000000   ;LVD interrupt acknowledge
mLVDIE:     equ   %00100000   ;LVD interrupt enable
mLVDRE:     equ   %00010000   ;LVD reset enable (write once bit)
mLVDSE:     equ   %00001000   ;LDV stop enable (write once bit)
mLVDE:      equ   %00000100   ;LVD enable (write once bit)

SPMSC2:     equ   $180A       ;System power management status and control 2 register
; bit position masks
mLVWF:      equ   %10000000   ;low voltage warning flag
mLVWACK:    equ   %01000000   ;low voltage warning acknowledge
mLVDV:      equ   %00100000   ;low voltage detect voltage select
mLVWV:      equ   %00010000   ;low voltage warning voltage select
mPPDF:      equ   %00001000   ;partial power down flag
mPPDACK:    equ   %00000100   ;partial power down acknowledge
mPDC:       equ   %00000010   ;power down control
mPPDC:      equ   %00000001   ;partial power down control

;****  Debug Module (DBG)  ******************************************************************
;*
DBGCAH:     equ   $1810       ;DBG comparator register A (high)
DBGCAL:     equ   $1811       ;DBG comparator register A (low)
DBGCBH:     equ   $1812       ;DBG comparator register B (high)
DBGCBL:     equ   $1813       ;DBG comparator register B (low)
DBGFH:      equ   $1814       ;DBG FIFO register (high)
DBGFL:      equ   $1815       ;DBG FIFO register (low)

DBGC:       equ   $1816       ;DBG control register
; bit position masks
mDBGEN:     equ   %10000000   ;debug module enable
mARM:       equ   %01000000   ;arm control
mTAG:       equ   %00100000   ;tag/force select
mBRKEN:     equ   %00010000   ;break enable
mRWA:       equ   %00001000   ;R/W compare A value
mRWAEN:     equ   %00000100   ;R/W compare A enable
mRWB:       equ   %00000010   ;R/W compare B value
mRWBEN:     equ   %00000001   ;R/W compare B enable

DBGT:       equ   $1817       ;DBG trigger register
; bit position masks
mTRGSEL:    equ   %10000000   ;trigger on opcode/access
mBEGIN:     equ   %01000000   ;begin/end trigger
mTRG3:      equ   %00001000   ;trigger mode bits
mTRG2:      equ   %00000100   ; "
mTRG1:      equ   %00000010   ; "
mTRG0:      equ   %00000001   ; "

DBGS:       equ   $1818       ;DBG status register
; bit position masks
mAF:        equ   %10000000   ;trigger A match flag
mBF:        equ   %01000000   ;trigger B match flag
mARMF:      equ   %00100000   ;arm flag
mCNT3:      equ   %00001000   ;count of items in FIFO (high)
mCNT2:      equ   %00000100   ; "
mCNT1:      equ   %00000010   ; "
mCNT0:      equ   %00000001   ;count of items in FIFO (low)

;****  Flash Module (FLASH)  ****************************************************************
;*
FCDIV:      equ   $1820       ;Flash clock divider register
; bit position masks
mDIVLD:     equ   %10000000   ;clock divider loaded
mPRDIV8:    equ   %01000000   ;enable prescale by 8
mDIV5:      equ   %00100000   ;flash clock divider bits (high)
mDIV4:      equ   %00010000   ; "
mDIV3:      equ   %00001000   ; "
mDIV2:      equ   %00000100   ; "
mDIV1:      equ   %00000010   ; "
mDIV0:      equ   %00000001   ;flash clock divider bits (low)

FOPT:       equ   $1821       ;Flash options register
; bit position masks
mKEYEN:     equ   %10000000   ;enable backdoor key to security
mFNORED     equ   %01000000   ;Vector redirection enable
mSEC01:     equ   %00000010   ;security state code (high)
mSEC00:     equ   %00000001   ;security state code (low)

FCNFG:      equ   $1823       ;Flash configuration register
; bit position masks
mKEYACC:    equ   %00100000   ;enable security key writing

FPROT:      equ   $1824       ;Flash protection register
; bit position masks
mFPOPEN:    equ   %10000000   ;open unprotected flash for program/erase
mFPDIS:     equ   %01000000   ;flash protection disable
mFPS2:      equ   %00100000   ;flash protect size select (high)
mFPS1:      equ   %00010000   ;flash protect size select
mFPS0:      equ   %00001000   ;flash protect size select (low)

FSTAT:      equ   $1825       ;Flash status register
; bit position masks
mFCBEF:     equ   %10000000   ;flash command buffer empty flag
mFCCF:      equ   %01000000   ;flash command complete flag
mFPVIOL:    equ   %00100000   ;flash protection violation
mFACCERR:   equ   %00010000   ;flash access error
mFBLANK:    equ   %00000100   ;flash verified as all blank (erased =$ff) flag

FCMD:       equ   $1826       ;Flash command register
; bit position masks
mFCMD7:     equ   %10000000   ;Flash command (high)
mFCMD6:     equ   %01000000   ; "
mFCMD5:     equ   %00100000   ; "
mFCMD4:     equ   %00010000   ; "
mFCMD3:     equ   %00001000   ; "
mFCMD2:     equ   %00000100   ; "
mFCMD1:     equ   %00000010   ; "
mFCMD0:     equ   %00000001   ;Flash command (low)
; command codes
mBlank:     equ   $05         ;Blank Check command
mByteProg:  equ   $20         ;Byte Program command
mBurstProg: equ   $25         ;Burst Program command
mPageErase: equ   $40         ;Page Erase command
mMassErase: equ   $41         ;Mass Erase command

;****  Flash non-volatile register images  **************************************************
;*
NVBACKKEY:  equ   $FFB0       ;8-byte backdoor comparison key
; comparison key in $FFB0 through $FFB7

; following 2 registers transfered from flash to working regs at reset

;NVPROT:     equ   $FFBD       ;NV flash protection byte
; NVPROT transfers to FPROT on reset

NVICGTRIM:  equ   $FFBE       ;NV ICG Trim Setting
; ICG trim value measured during factory test. User software optionally
; copies to ICGTRM during initialization.

;NVOPT:      equ   $FFBF       ;NV flash options byte
; NVFEOPT transfers to FOPT on reset

;****  END  *****************************************************