📄 9s08gb60.inc
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mT6: equ %01000000 ; "
mT5: equ %00100000 ; "
mT4: equ %00010000 ; "
mT3: equ %00001000 ; "
mT2: equ %00000100 ; "
mT1: equ %00000010 ; "
mT0: equ %00000001 ; "
;**** Serial Peripheral Interface (SPI) ***************************************************
;*
SPIC1: equ $28 ;SPI control register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SPIE: equ 7 ;(bit #7) SPI interrupt enable
SPE: equ 6 ;(bit #6) SPI enable
SPTIE: equ 5 ;(bit #5) Tx error interrupt enable
MSTR: equ 4 ;(bit #4) master/slave
CPOL: equ 3 ;(bit #3) clock polarity
CPHA: equ 2 ;(bit #2) clock phase
SSOE: equ 1 ;(bit #1) SS output enable
LSBFE: equ 0 ;(bit #0) LSB-first enable
; bit position masks
mSPIE: equ %10000000 ;SPI interrupt enable
mSPE: equ %01000000 ;SPI enable
mSPTIE: equ %00100000 ;SPI Tx error interrupt enable
mMSTR: equ %00010000 ;master/slave
mCPOL: equ %00001000 ;clock polarity
mCPHA: equ %00000100 ;clock phase
mSSOE: equ %00000010 ;slave select output enable
mLSBFE: equ %00000001 ;LSB-first enable
SPIC2: equ $29 ;SPI control register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
MODFEN: equ 4 ;(bit #4) mode fault enable
BIDIROE: equ 3 ;(bit #3) bi-directional enable
SPISWAI: equ 1 ;(bit #1) SPI stops in wait
SPC0: equ 0 ;(bit #0) SPI pin 0 control
; bit position masks
mMODFEN: equ %00010000 ;mode fault enable
mBIDIROE: equ %00001000 ;bi-directional operation enable
mSPISWAI: equ %00000010 ;SPI stops in wait mode
mSPC0: equ %00000001 ;SPI pin 0 control
SPIBR: equ $2A ;SPI baud rate select
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SPPR2: equ 6 ;(bit #6) SPI baud rate prescale
SPPR1: equ 5 ;(bit #5) "
SPPR0: equ 4 ;(bit #4) "
SPR2: equ 2 ;(bit #2) SPI rate selact
SPR1: equ 1 ;(bit #1) "
SPR0: equ 0 ;(bit #0) "
; bit position masks
mSPPR2: equ %01000000 ;SPI baud rate prescale
mSPPR1: equ %00100000 ; "
mSPPR0: equ %00010000 ; "
mSPR2: equ %00000100 ;SPI rate select
mSPR1: equ %00000010 ; "
mSPR0: equ %00000001 ; "
SPIS: equ $2B ;SPI status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SPRF: equ 7 ;(bit #7) SPI Rx full flag
SPTEF: equ 5 ;(bit #5) SPI Tx error flag
MODF: equ 4 ;(bit #4) mode fault flag
; bit position masks
mSPRF: equ %10000000 ;SPI receive buffer full flag
mSPTEF: equ %00100000 ;SPI Tx error flag?
mMODF: equ %00010000 ;mode fault flag
SPID: equ $2D ;SPI data register
;**** Analog-to-Digital Converter Module (ATD) ********************************************
;*;
ATDC: equ $50 ;atd control tegister
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
ATDPU: equ 7 ;(bit #7) ATD power up
DJM: equ 6 ;(bit #6) justification mode; rt/left
RES8: equ 5 ;(bit #5) ATD resolution select
SGN: equ 4 ;(bit #4) signed result select
PRS3: equ 3 ;(bit #3) prescaler rate select (high)
PRS2: equ 2 ;(bit #2) prescaler rate select
PRS1: equ 1 ;(bit #1) prescaler rate select
PRS0: equ 0 ;(bit #0) prescaler rate select (low)
; bit position masks
mATDPU: equ %10000000 ;ATD power up
mDJM: equ %01000000 ;data justification mode; right/left
mRES8: equ %00100000 ;ATD resolution select
mSGN: equ %00010000 ;signed result select
mPRS3: equ %00001000 ;prescaler rate select (high)
mPRS2: equ %00000100 ;prescaler rate select
mPRS1: equ %00000010 ;prescaler rate select
mPRS0: equ %00000001 ;prescaler rate select (low)
ATDSC: equ $51 ;atd ststus and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CCF: equ 7 ;(bit #7) conversion complete flag
ATDIE: equ 6 ;(bit #6) ATD interrupt enable
ATDCO: equ 5 ;(bit #5) ATD continuous conversion
ATDCH4: equ 4 ;(bit #4) ATD input channel select (high)
ATDCH3: equ 3 ;(bit #3) ATD input channel select
ATDCH2: equ 2 ;(bit #2) ATD input channel select
ATDCH1: equ 1 ;(bit #1) ATD input channel select
ATDCH0: equ 0 ;(bit #0) ATD input channel select (low)
; bit position masks
mCCF: equ %10000000 ;conversion complete flag
mATDIE: equ %01000000 ;ATD interrupt enable
mATDCO: equ %00100000 ;ATD continuous conversion
mATDCH4: equ %00010000 ;ATD input channel select (high)
mATDCH3: equ %00001000 ;prescaler rate select
mATDCH2: equ %00000100 ;prescaler rate select
mATDCH1: equ %00000010 ;prescaler rate select
mATDCH0: equ %00000001 ;prescaler rate select (low)
ATDPE: equ $54 ;ATD pin enable register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
ATDPE7: equ 7 ;(bit #7)
ATDPE6: equ 6 ;(bit #6)
ATDPE5: equ 5 ;(bit #5)
ATDPE4: equ 4 ;(bit #4)
ATDPE3: equ 3 ;(bit #3)
ATDPE2: equ 2 ;(bit #2)
ATDPE1: equ 1 ;(bit #1)
ATDPE0: equ 0 ;(bit #0)
; bit position masks
mATDPE7: equ %10000000 ;ATDPE bit 7
mATDPE6: equ %01000000 ;ATDPE bit 6
mATDPE5: equ %00100000 ;ATDPE bit 5
mATDPE4: equ %00010000 ;ATDPE bit 4
mATDPE3: equ %00001000 ;ATDPE bit 3
mATDPE2: equ %00000100 ;ATDPE bit 2
mATDPE1: equ %00000010 ;ATDPE bit 1
mATDPE0: equ %00000001 ;ATDPE bit 0
ATDRH: equ $52 ;ATD result register (high)
ATDRL: equ $53 ;ATD result register (low)
;**** Inter-Integrated Circuit Module (IIC) ************************************************
;*;
IICA: equ $58 ;IIC address register
IICF: equ $59 ;IIC frequency divider register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
MULT1: equ 7 ;(bit #7) IIC multiply factor (high)
MULT0: equ 6 ;(bit #6) IIC multiply factor (low)
ICR5: equ 5 ;(bit #5) IIC Divider and Hold bit-5
ICR4: equ 4 ;(bit #4) IIC Divider and Hold bit-4
ICR3: equ 3 ;(bit #3) IIC Divider and Hold bit-3
ICR2: equ 2 ;(bit #2) IIC Divider and Hold bit-2
ICR1: equ 1 ;(bit #1) IIC Divider and Hold bit-1
ICR0: equ 0 ;(bit #0) IIC Divider and Hold bit-0
; bit position masks
mMULT1: equ %10000000 ;IIC multiply factor (high)
mMULT0: equ %01000000 ;IIC multiply factor (low)
mICR5: equ %00100000 ;IIC Divider and Hold bit-5
mICR4: equ %00010000 ;IIC Divider and Hold bit-4
mICR3: equ %00001000 ;IIC Divider and Hold bit-3
mICR2: equ %00000100 ;IIC Divider and Hold bit-2
mICR1: equ %00000010 ;IIC Divider and Hold bit-1
mICR0: equ %00000001 ;IIC Divider and Hold bit-0
IICC: equ $5A ;IIC control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IICEN: equ 7 ;(bit #7) IIC enable bit
IICIE: equ 6 ;(bit #6) IIC interrupt enable bit
MST: equ 5 ;(bit #5) IIC master mode select bit
TX: equ 4 ;(bit #4) IIC transmit mode select bit
TXAK: equ 3 ;(bit #3) IIC transmit acknowledge bit
RSTA: equ 2 ;(bit #2) IIC repeat start bit
; bit position masks
mIICEN: equ %10000000 ;IIC enable
mIICIE: equ %01000000 ;IIC interrupt enable bit
mMST: equ %00100000 ;IIC master mode select bit
mTX: equ %00010000 ;IIC transmit mode select bit
mTXAK: equ %00001000 ;IIC transmit acknowledge bit
mRSTA: equ %00000100 ;IIC repeat start bit
IICS: equ $5B ;IIC status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TCF: equ 7 ;(bit #7) IIC transfer complete flag bit
IAAS: equ 6 ;(bit #6) IIC addressed as slave bit
BUSY: equ 5 ;(bit #5) IIC bus busy bit
ARBL: equ 4 ;(bit #4) IIC arbitration lost bit
SRW: equ 2 ;(bit #2) IIC slave read/write bit
IICIF: equ 1 ;(bit #1) IIC interrupt flag bit
RXAK: equ 0 ;(bit #0) IIC receive acknowledge bit
; bit position masks
mTCF: equ %10000000 ;IIC transfer complete flag bit
mIAAS: equ %01000000 ;IIC addressed as slave bit
mBUSY: equ %00100000 ;IIC bus busy bit
mARBL: equ %00010000 ;IIC arbitration lost bit
mSRW: equ %00000100 ;IIC slave read/write bit
mIICIF: equ %00000010 ;IIC interrupt flag bit
mRXAK: equ %00000001 ;IIC receive acknowledge bit
IICD: equ $5C ;IIC data I/O register bits 7:0
;**** Timer/PWM Module 1 (TPM1) ***** TPM1 has 3 channels *********************************
;**** Timer/PWM Module 2 (TPM2) ***** TPM2 has 5 channels *********************************
;*
TPM1SC: equ $30 ;TPM1 status and control register
TPM2SC: equ $60 ;TPM2 status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TOF: equ 7 ;(bit #7) tomer overflow flag
TOIE: equ 6 ;(bit #6) TOF interrupt enable
CPWMS: equ 5 ;(bit #5) centered PWM select
CLKSB: equ 4 ;(bit #4) clock select bits
CLKSA: equ 3 ;(bit #3) "
PS2: equ 2 ;(bit #2) prescaler bits
PS1: equ 1 ;(bit #1) "
PS0: equ 0 ;(bit #0) "
; bit position masks
mTOF: equ %10000000 ;timer overflow flag
mTOIE: equ %01000000 ;timer overflow interrupt enable
mCPWMS: equ %00100000 ;center-aligned PWM select
mCLKSB: equ %00010000 ;clock source select bits
mCLKSA: equ %00001000 ; "
mPS2: equ %00000100 ;prescaler bits
mPS1: equ %00000010 ; "
mPS0: equ %00000001 ; "
TPM1CNTH: equ $31 ;TPM1 counter (high half)
TPM1CNTL: equ $32 ;TPM1 counter (low half)
TPM1MODH: equ $33 ;TPM1 modulo register (high half)
TPM1MODL: equ $34 ;TPM1 modulo register(low half)
TPM2CNTH: equ $61 ;TPM2 counter (high half)
TPM2CNTL: equ $62 ;TPM2 counter (low half)
TPM2MODH: equ $63 ;TPM2 modulo register (high half)
TPM2MODL: equ $64 ;TPM2 modulo register(low half)
TPM1C0SC: equ $35 ;TPM1 channel 0 status and control
TPM2C0SC: equ $65 ;TPM2 channel 0 status and control
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH0F: equ 7 ;(bit #7) channel 0 flag
CH0IE: equ 6 ;(bit #6) ch 0 interrupt enable
MS0B: equ 5 ;(bit #5) mode select B
MS0A: equ 4 ;(bit #4) mode select A
ELS0B: equ 3 ;(bit #3) edge/level select B
ELS0A: equ 2 ;(bit #2) edge/level select A
; bit position masks
mCH0F: equ %10000000 ;channel 0 flag
mCH0IE: equ %01000000 ;ch 0 interrupt enable
mMS0B: equ %00100000 ;mode select B
mMS0A: equ %00010000 ;mode select A
mELS0B: equ %00001000 ;edge/level select B
mELS0A: equ %00000100 ;edge/level select A
TPM1C0VH: equ $36 ;TPM1 channel 0 value register (high)
TPM1C0VL: equ $37 ;TPM1 channel 0 value register (low)
TPM2C0VH: equ $66 ;TPM2 channel 0 value register (high)
TPM2C0VL: equ $67 ;TPM2 channel 0 value register (low)
TPM1C1SC: equ $38 ;TPM1 channel 1 status and control
TPM2C1SC: equ $68 ;TPM2 channel 1 status and control
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH1F: equ 7 ;(bit #7) channel 1 flag
CH1IE: equ 6 ;(bit #6) ch 1 interrupt enable
MS1B: equ 5 ;(bit #5) mode select B
MS1A: equ 4 ;(bit #4) mode select A
ELS1B: equ 3 ;(bit #3) edge/level select B
ELS1A: equ 2 ;(bit #2) edge/level select A
; bit position masks
mCH1F: equ %10000000 ;channel 1 flag
mCH1IE: equ %01000000 ;ch 1 interrupt enable
mMS1B: equ %00100000 ;mode select B
mMS1A: equ %00010000 ;mode select A
mELS1B: equ %00001000 ;edge/level select B
mELS1A: equ %00000100 ;edge/level select A
TPM1C1VH: equ $39 ;TPM1 channel 1 value register (high)
TPM1C1VL: equ $3A ;TPM1 channel 1 value register (low)
TPM2C1VH: equ $69 ;TPM2 channel 1 value register (high)
TPM2C1VL: equ $6A ;TPM2 channel 1 value register (low)
TPM1C2SC: equ $3B ;TPM1 channel 2 status and control
TPM2C2SC: equ $6B ;TPM2 channel 2 status and control
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH2F: equ 7 ;(bit #7) channel 2 flag
CH2IE: equ 6 ;(bit #6) ch 2 interrupt enable
MS2B: equ 5 ;(bit #5) mode select B
MS2A: equ 4 ;(bit #4) mode select A
ELS2B: equ 3 ;(bit #3) edge/level select B
ELS2A: equ 2 ;(bit #2) edge/level select A
; bit position masks
mCH2F: equ %10000000 ;channel 2 flag
mCH2IE: equ %01000000 ;ch 2 interrupt enable
mMS2B: equ %00100000 ;mode select B
mMS2A: equ %00010000 ;mode select A
mELS2B: equ %00001000 ;edge/level select B
mELS2A: equ %00000100 ;edge/level select A
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