📄 9s08gb60.inc
字号:
PTGD0: equ 0 ;bit #0
; bit position masks
mPTGD7: equ %10000000 ;port G bit 7
mPTGD6: equ %01000000 ;port G bit 6
mPTGD5: equ %00100000 ;port G bit 5
mPTGD4: equ %00010000 ;port G bit 4
mPTGD3: equ %00001000 ;port G bit 3
mPTGD2: equ %00000100 ;port G bit 2
mPTGD1: equ %00000010 ;port G bit 1
mPTGD0: equ %00000001 ;port G bit 0
PTGPE: equ $45 ;I/O port G pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTGPE7: equ 7 ;bit #7
PTGPE6: equ 6 ;bit #6
PTGPE5: equ 5 ;bit #5
PTGPE4: equ 4 ;bit #4
PTGPE3: equ 3 ;bit #3
PTGPE2: equ 2 ;bit #2
PTGPE1: equ 1 ;bit #1
PTGPE0: equ 0 ;bit #0
; bit position masks
mPTGPE7: equ %10000000 ;port G bit 7
mPTGPE6: equ %01000000 ;port G bit 6
mPTGPE5: equ %00100000 ;port G bit 5
mPTGPE4: equ %00010000 ;port G bit 4
mPTGPE3: equ %00001000 ;port G bit 3
mPTGPE2: equ %00000100 ;port G bit 2
mPTGPE1: equ %00000010 ;port G bit 1
mPTGPE0: equ %00000001 ;port G bit 0
PTGSE: equ $46 ;I/O port G slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTGSE7: equ 7 ;bit #7
PTGSE6: equ 6 ;bit #6
PTGSE5: equ 5 ;bit #5
PTGSE4: equ 4 ;bit #4
PTGSE3: equ 3 ;bit #3
PTGSE2: equ 2 ;bit #2
PTGSE1: equ 1 ;bit #1
PTGSE0: equ 0 ;bit #0
; bit position masks
mPTGSE7: equ %10000000 ;port G bit 7
mPTGSE6: equ %01000000 ;port G bit 6
mPTGSE5: equ %00100000 ;port G bit 5
mPTGSE4: equ %00010000 ;port G bit 4
mPTGSE3: equ %00001000 ;port G bit 3
mPTGSE2: equ %00000100 ;port G bit 2
mPTGSE1: equ %00000010 ;port G bit 1
mPTGSE0: equ %00000001 ;port G bit 0
PTGDD: equ $47 ;I/O port G data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTGDD7: equ 7 ;bit #7
PTGDD6: equ 6 ;bit #6
PTGDD5: equ 5 ;bit #5
PTGDD4: equ 4 ;bit #4
PTGDD3: equ 3 ;bit #3
PTGDD2: equ 2 ;bit #2
PTGDD1: equ 1 ;bit #1
PTGDD0: equ 0 ;bit #0
; bit position masks
mPTGDD7: equ %10000000 ;port G bit 7
mPTGDD6: equ %01000000 ;port G bit 6
mPTGDD5: equ %00100000 ;port G bit 5
mPTGDD4: equ %00010000 ;port G bit 4
mPTGDD3: equ %00001000 ;port G bit 3
mPTGDD2: equ %00000100 ;port G bit 2
mPTGDD1: equ %00000010 ;port G bit 1
mPTGDD0: equ %00000001 ;port G bit 0
;**** Interrupt Request Module (IRQ) ******************************************************
;*
IRQSC: equ $14 ;IRQ status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IRQEDG: equ 5 ;(bit #5) IRQ pin edge sensitivity
IRQPE: equ 4 ;(bit #4) IRQ pin enable (PTB5)
IRQF: equ 3 ;(bit #3) IRQ flag
IRQACK: equ 2 ;(bit #2) acknowledge IRQ flag
IRQIE: equ 1 ;(bit #1) IRQ pin interrupt enable
IRQMOD: equ 0 ;(bit #0) IRQ mode
; bit position masks
mIRQEDG: equ %00100000 ;IRQ pin edge sensitivity
mIRQPE: equ %00010000 ;IRQ pin enable (PTB5)
mIRQF: equ %00001000 ;IRQ flag
mIRQACK: equ %00000100 ;acknowledge IRQ flag
mIRQIE: equ %00000010 ;IRQ pin interrupt enable
mIRQMOD: equ %00000001 ;IRQ mode
;**** Keyboard Interrupt Module (KBI) *****************************************************
;*
KBISC: equ $16 ;KBI status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
KBEDG7: equ 7 ;rise-hi/fall-low for KBIP7 pin
KBEDG6: equ 6 ;rise-hi/fall-low for KBIP6 pin
KBEDG5: equ 5 ;rise-hi/fall-low for KBIP5 pin
KBEDG4: equ 4 ;rise-hi/fall-low for KBIP4 pin
KBF: equ 3 ;KBI flag
KBACK: equ 2 ;acknowledge
KBIE: equ 1 ;KBI interrupt enable
KBIMOD: equ 0 ;KBI mode select
; bit position masks
mKBEDG7: equ %10000000 ;rise-hi/fall-low for KBIP7 pin
mKBEDG6: equ %01000000 ;rise-hi/fall-low for KBIP6 pin
mKBEDG5: equ %00100000 ;rise-hi/fall-low for KBIP5 pin
mKBEDG4: equ %00010000 ;rise-hi/fall-low for KBIP4 pin
mKBF: equ %00001000 ;KBI flag
mKBACK: equ %00000100 ;acknowledge
mKBIE: equ %00000010 ;KBI interrupt enable
mKBIMOD: equ %00000001 ;KBI mode select
KBIPE: equ $17 ;KBI pin enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
KBIPE7: equ 7 ;bit #7
KBIPE6: equ 6 ;bit #6
KBIPE5: equ 5 ;bit #5
KBIPE4: equ 4 ;bit #4
KBIPE3: equ 3 ;bit #3
KBIPE2: equ 2 ;bit #2
KBIPE1: equ 1 ;bit #1
KBIPE0: equ 0 ;bit #0
; bit position masks
mKBIPE7: equ %10000000 ;port A bit 7
mKBIPE6: equ %01000000 ;port A bit 6
mKBIPE5: equ %00100000 ;port A bit 5
mKBIPE4: equ %00010000 ;port A bit 4
mKBIPE3: equ %00001000 ;port A bit 3
mKBIPE2: equ %00000100 ;port A bit 2
mKBIPE1: equ %00000010 ;port A bit 1
mKBIPE0: equ %00000001 ;port A bit 0
;**** Serial Communications Interface 1&2 (SCI1 & SCI2) ***********************************
;*
SCI1BDH: equ $18 ;SCI1 baud rate register (high)
SCI2BDH: equ $20 ;SCI2 baud rate register (high)
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SBR12: equ 4 ;(bit #4) baud divide (high)
SBR11: equ 3 ;(bit #3) "
SBR10: equ 2 ;(bit #2) "
SBR9: equ 1 ;(bit #1) "
SBR8: equ 0 ;(bit #0) "
; bit position masks
mSBR12: equ %00010000 ;high bits of baud rate divider
mSBR11: equ %00001000 ; "
mSBR10: equ %00000100 ; "
mSBR9: equ %00000010 ; "
mSBR8: equ %00000001 ; "
SCI1BDL: equ $19 ;SCI1 baud rate register (low byte)
SCI2BDL: equ $21 ;SCI2 baud rate register (low byte)
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SBR7: equ 7 ;(bit #7) baud divide (low)
SBR6: equ 6 ;(bit #6) "
SBR5: equ 5 ;(bit #5) "
SBR4: equ 4 ;(bit #4) "
SBR3: equ 3 ;(bit #3) "
SBR2: equ 2 ;(bit #2) "
SBR1: equ 1 ;(bit #1) "
SBR0: equ 0 ;(bit #0) "
; bit position masks
mSBR7: equ %10000000 ;low byte of baud rate divider
mSBR6: equ %01000000 ; "
mSBR5: equ %00100000 ; "
mSBR4: equ %00010000 ; "
mSBR3: equ %00001000 ; "
mSBR2: equ %00000100 ; "
mSBR1: equ %00000010 ; "
mSBR0: equ %00000001 ; "
SCI1C1: equ $1A ;SCI1 control register 1
SCI2C1: equ $22 ;SCI2 control register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
LOOPS: equ 7 ;(bit #7) loopback mode
SCISWAI: equ 6 ;(bit #6) SCI stop in wait
RSRC: equ 5 ;(bit #5) receiver source
M: equ 4 ;(bit #4) 9/8 bit data
WAKE: equ 3 ;(bit #3) wake by addr mark/idle
ILT: equ 2 ;(bit #2) idle line type; stop/start
PE: equ 1 ;(bit #1) parity enable
PT: equ 0 ;(bit #0) parity type
; bit position masks
mLOOPS: equ %10000000 ;loopback mode select
mSCISWAI: equ %01000000 ;SCI stops in wait mode
mRSRC: equ %00100000 ;receiver source
mM: equ %00010000 ;9/8 bit data
mWAKE: equ %00001000 ;wakeup by addr mark/idle
mILT: equ %00000100 ;idle line type; after stop/start
mPE: equ %00000010 ;parity enable
mPT: equ %00000001 ;parity type even/odd
SCI1C2: equ $1B ;SCI1 control register 2
SCI2C2: equ $23 ;SCI2 control register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TIE: equ 7 ;(bit #7) transmit interrupt enable
TCIE: equ 6 ;(bit #6) TC interrupt enable
RIE: equ 5 ;(bit #5) receive interrupt enable
ILIE: equ 4 ;(bit #4) idle line interrupt enable
TE: equ 3 ;(bit #3) transmitter enable
RE: equ 2 ;(bit #2) receiver enable
RWU: equ 1 ;(bit #1) receiver wakeup engage
SBK: equ 0 ;(bit #0) send break
; bit position masks
mTIE: equ %10000000 ;transmit interrupt (TDRE) enable
mTCIE: equ %01000000 ;transmit complete interrupt enable
mRIE: equ %00100000 ;receive interrupt (RDRF) enable
mILIE: equ %00010000 ;idle line interrupt (ILIE) enable
mTE: equ %00001000 ;transmitter enable
mRE: equ %00000100 ;receiver enable
mRWU: equ %00000010 ;receiver wakeup engage
mSBK: equ %00000001 ;send break characters
SCI1S1: equ $1C ;SCI1 status register 1
SCI2S1: equ $24 ;SCI2 status register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TDRE: equ 7 ;(bit #7) Tx data register empty
TC: equ 6 ;(bit #6) transmit complete
RDRF: equ 5 ;(bit #5) Rx data register full
IDLE: equ 4 ;(bit #4) idle line detected
OR: equ 3 ;(bit #3) Rx over run
NF: equ 2 ;(bit #2) Rx noise flag
FE: equ 1 ;(bit #1) Rx framing error
PF: equ 0 ;(bit #0) Rx parity failed
; bit position masks
mTDRE: equ %10000000 ;transmit data register empty
mTC: equ %01000000 ;transmit complete
mRDRF: equ %00100000 ;receive data register full
mIDLE: equ %00010000 ;idle line detected
mOR: equ %00001000 ;receiver over run
mNF: equ %00000100 ;receiver noise flag
mFE: equ %00000010 ;receiver framing error
mPF: equ %00000001 ;received parity failed
SCI1S2: equ $1D ;SCI1 status register 2
SCI2S2: equ $25 ;SCI2 status register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
RAF: equ 0 ;(bit #0) Rx active flag
; bit position masks
mRAF: equ %00000001 ;receiver active flag
SCI1C3: equ $1E ;SCI1 control register 3
SCI2C3: equ $26 ;SCI2 control register 3
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
R8: equ 7 ;(bit #7) 9th Rx bit
T8: equ 6 ;(bit #6) 9th Tx bit
TXDIR: equ 5 ;(bit #5) TxD pin direction?
ORIE: equ 3 ;(bit #3) Rx over run int. enable
NEIE: equ 2 ;(bit #2) Rx noise flag int. enable
FEIE: equ 1 ;(bit #1) Rx framing error int. enable
PEIE: equ 0 ;(bit #0) Rx parity error int. enable
; bit position masks
mR8: equ %10000000 ;9th receive data bit
mT8: equ %01000000 ;9th transmit data bit
mTXDIR: equ %00100000 ;transmit pin direction?
mORIE: equ %00001000 ;receiver over run int. enable
mNEIE: equ %00000100 ;receiver noise flag int. enable
mFEIE: equ %00000010 ;receiver framing error int. enable
mPEIE: equ %00000001 ;received parity error int. enable
SCI1D: equ $1F ;SCI1 data register (low byte)
SCI2D: equ $27 ;SCI2 data register (low byte)
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
; read-only Rx data buffer
R7: equ 7 ;(bit #7) receive data bits
R6: equ 6 ;(bit #6) "
R5: equ 5 ;(bit #5) "
R4: equ 4 ;(bit #4) "
R3: equ 3 ;(bit #3) "
R2: equ 2 ;(bit #2) "
R1: equ 1 ;(bit #1) "
R0: equ 0 ;(bit #0) "
; write-only Tx data buffer
T7: equ 7 ;(bit #7) transmit data bits
T6: equ 6 ;(bit #6) "
T5: equ 5 ;(bit #5) "
T4: equ 4 ;(bit #4) "
T3: equ 3 ;(bit #3) "
T2: equ 2 ;(bit #2) "
T1: equ 1 ;(bit #1) "
T0: equ 0 ;(bit #0) "
; bit position masks
; read-only Rx data buffer
mR7: equ %10000000 ;receive data bits
mR6: equ %01000000 ; "
mR5: equ %00100000 ; "
mR4: equ %00010000 ; "
mR3: equ %00001000 ; "
mR2: equ %00000100 ; "
mR1: equ %00000010 ; "
mR0: equ %00000001 ; "
; write-only Tx data buffer
mT7: equ %10000000 ;transmit data bits
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -