📄 9s08gb60.inc
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PTCSE: equ $0A ;I/O port C slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTCSE7: equ 7 ;bit #7
PTCSE6: equ 6 ;bit #6
PTCSE5: equ 5 ;bit #5
PTCSE4: equ 4 ;bit #4
PTCSE3: equ 3 ;bit #3
PTCSE2: equ 2 ;bit #2
PTCSE1: equ 1 ;bit #1
PTCSE0: equ 0 ;bit #0
; bit position masks
mPTCSE7: equ %10000000 ;port C bit 7
mPTCSE6: equ %01000000 ;port C bit 6
mPTCSE5: equ %00100000 ;port C bit 5
mPTCSE4: equ %00010000 ;port C bit 4
mPTCSE3: equ %00001000 ;port C bit 3
mPTCSE2: equ %00000100 ;port C bit 2
mPTCSE1: equ %00000010 ;port C bit 1
mPTCSE0: equ %00000001 ;port C bit 0
PTCDD: equ $0B ;I/O port C data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTCDD7: equ 7 ;bit #7
PTCDD6: equ 6 ;bit #6
PTCDD5: equ 5 ;bit #5
PTCDD4: equ 4 ;bit #4
PTCDD3: equ 3 ;bit #3
PTCDD2: equ 2 ;bit #2
PTCDD1: equ 1 ;bit #1
PTCDD0: equ 0 ;bit #0
; bit position masks
mPTCDD7: equ %10000000 ;port C bit 7
mPTCDD6: equ %01000000 ;port C bit 6
mPTCDD5: equ %00100000 ;port C bit 5
mPTCDD4: equ %00010000 ;port C bit 4
mPTCDD3: equ %00001000 ;port C bit 3
mPTCDD2: equ %00000100 ;port C bit 2
mPTCDD1: equ %00000010 ;port C bit 1
mPTCDD0: equ %00000001 ;port C bit 0
PTDD: equ $0C ;I/O port D data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTDD7: equ 7 ;bit #7
PTDD6: equ 6 ;bit #6
PTDD5: equ 5 ;bit #5
PTDD4: equ 4 ;bit #4
PTDD3: equ 3 ;bit #3
PTDD2: equ 2 ;bit #2
PTDD1: equ 1 ;bit #1
PTDD0: equ 0 ;bit #0
; bit position masks
mPTDD7: equ %10000000 ;port D bit 7
mPTDD6: equ %01000000 ;port D bit 6
mPTDD5: equ %00100000 ;port D bit 5
mPTDD4: equ %00010000 ;port D bit 4
mPTDD3: equ %00001000 ;port D bit 3
mPTDD2: equ %00000100 ;port D bit 2
mPTDD1: equ %00000010 ;port D bit 1
mPTDD0: equ %00000001 ;port D bit 0
PTDPE: equ $0D ;I/O port D pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTDPE7: equ 7 ;bit #7
PTDPE6: equ 6 ;bit #6
PTDPE5: equ 5 ;bit #5
PTDPE4: equ 4 ;bit #4
PTDPE3: equ 3 ;bit #3
PTDPE2: equ 2 ;bit #2
PTDPE1: equ 1 ;bit #1
PTDPE0: equ 0 ;bit #0
; bit position masks
mPTDPE7: equ %10000000 ;port D bit 7
mPTDPE6: equ %01000000 ;port D bit 6
mPTDPE5: equ %00100000 ;port D bit 5
mPTDPE4: equ %00010000 ;port D bit 4
mPTDPE3: equ %00001000 ;port D bit 3
mPTDPE2: equ %00000100 ;port D bit 2
mPTDPE1: equ %00000010 ;port D bit 1
mPTDPE0: equ %00000001 ;port D bit 0
PTDSE: equ $0E ;I/O port D slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTDSE7: equ 7 ;bit #7
PTDSE6: equ 6 ;bit #6
PTDSE5: equ 5 ;bit #5
PTDSE4: equ 4 ;bit #4
PTDSE3: equ 3 ;bit #3
PTDSE2: equ 2 ;bit #2
PTDSE1: equ 1 ;bit #1
PTDSE0: equ 0 ;bit #0
; bit position masks
mPTDSE7: equ %10000000 ;port D bit 7
mPTDSE6: equ %01000000 ;port D bit 6
mPTDSE5: equ %00100000 ;port D bit 5
mPTDSE4: equ %00010000 ;port D bit 4
mPTDSE3: equ %00001000 ;port D bit 3
mPTDSE2: equ %00000100 ;port D bit 2
mPTDSE1: equ %00000010 ;port D bit 1
mPTDSE0: equ %00000001 ;port D bit 0
PTDDD: equ $0F ;I/O port D data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTDDD7: equ 7 ;bit #7
PTDDD6: equ 6 ;bit #6
PTDDD5: equ 5 ;bit #5
PTDDD4: equ 4 ;bit #4
PTDDD3: equ 3 ;bit #3
PTDDD2: equ 2 ;bit #2
PTDDD1: equ 1 ;bit #1
PTDDD0: equ 0 ;bit #0
; bit position masks
mPTDDD7: equ %10000000 ;port D bit 7
mPTDDD6: equ %01000000 ;port D bit 6
mPTDDD5: equ %00100000 ;port D bit 5
mPTDDD4: equ %00010000 ;port D bit 4
mPTDDD3: equ %00001000 ;port D bit 3
mPTDDD2: equ %00000100 ;port D bit 2
mPTDDD1: equ %00000010 ;port D bit 1
mPTDDD0: equ %00000001 ;port D bit 0
PTED: equ $10 ;I/O port E data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTED7: equ 7 ;bit #7
PTED6: equ 6 ;bit #6
PTED5: equ 5 ;bit #5
PTED4: equ 4 ;bit #4
PTED3: equ 3 ;bit #3
PTED2: equ 2 ;bit #2
PTED1: equ 1 ;bit #1
PTED0: equ 0 ;bit #0
; bit position masks
mPTED7: equ %10000000 ;port E bit 7
mPTED6: equ %01000000 ;port E bit 6
mPTED5: equ %00100000 ;port E bit 5
mPTED4: equ %00010000 ;port E bit 4
mPTED3: equ %00001000 ;port E bit 3
mPTED2: equ %00000100 ;port E bit 2
mPTED1: equ %00000010 ;port E bit 1
mPTED0: equ %00000001 ;port E bit 0
PTEPE: equ $11 ;I/O port E pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTEPE7: equ 7 ;bit #7
PTEPE6: equ 6 ;bit #6
PTEPE5: equ 5 ;bit #5
PTEPE4: equ 4 ;bit #4
PTEPE3: equ 3 ;bit #3
PTEPE2: equ 2 ;bit #2
PTEPE1: equ 1 ;bit #1
PTEPE0: equ 0 ;bit #0
; bit position masks
mPTEPE7: equ %10000000 ;port E bit 7
mPTEPE6: equ %01000000 ;port E bit 6
mPTEPE5: equ %00100000 ;port E bit 5
mPTEPE4: equ %00010000 ;port E bit 4
mPTEPE3: equ %00001000 ;port E bit 3
mPTEPE2: equ %00000100 ;port E bit 2
mPTEPE1: equ %00000010 ;port E bit 1
mPTEPE0: equ %00000001 ;port E bit 0
PTESE: equ $12 ;I/O port E slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTESE7: equ 7 ;bit #7
PTESE6: equ 6 ;bit #6
PTESE5: equ 5 ;bit #5
PTESE4: equ 4 ;bit #4
PTESE3: equ 3 ;bit #3
PTESE2: equ 2 ;bit #2
PTESE1: equ 1 ;bit #1
PTESE0: equ 0 ;bit #0
; bit position masks
mPTESE7: equ %10000000 ;port E bit 7
mPTESE6: equ %01000000 ;port E bit 6
mPTESE5: equ %00100000 ;port E bit 5
mPTESE4: equ %00010000 ;port E bit 4
mPTESE3: equ %00001000 ;port E bit 3
mPTESE2: equ %00000100 ;port E bit 2
mPTESE1: equ %00000010 ;port E bit 1
mPTESE0: equ %00000001 ;port E bit 0
PTEDD: equ $13 ;I/O port E data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTEDD7: equ 7 ;bit #7
PTEDD6: equ 6 ;bit #6
PTEDD5: equ 5 ;bit #5
PTEDD4: equ 4 ;bit #4
PTEDD3: equ 3 ;bit #3
PTEDD2: equ 2 ;bit #2
PTEDD1: equ 1 ;bit #1
PTEDD0: equ 0 ;bit #0
; bit position masks
mPTEDD7: equ %10000000 ;port E bit 7
mPTEDD6: equ %01000000 ;port E bit 6
mPTEDD5: equ %00100000 ;port E bit 5
mPTEDD4: equ %00010000 ;port E bit 4
mPTEDD3: equ %00001000 ;port E bit 3
mPTEDD2: equ %00000100 ;port E bit 2
mPTEDD1: equ %00000010 ;port E bit 1
mPTEDD0: equ %00000001 ;port E bit 0
PTFD: equ $40 ;I/O port F data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTFD7: equ 7 ;bit #7
PTFD6: equ 6 ;bit #6
PTFD5: equ 5 ;bit #5
PTFD4: equ 4 ;bit #4
PTFD3: equ 3 ;bit #3
PTFD2: equ 2 ;bit #2
PTFD1: equ 1 ;bit #1
PTFD0: equ 0 ;bit #0
; bit position masks
mPTFD7: equ %10000000 ;port F bit 7
mPTFD6: equ %01000000 ;port F bit 6
mPTFD5: equ %00100000 ;port F bit 5
mPTFD4: equ %00010000 ;port F bit 4
mPTFD3: equ %00001000 ;port F bit 3
mPTFD2: equ %00000100 ;port F bit 2
mPTFD1: equ %00000010 ;port F bit 1
mPTFD0: equ %00000001 ;port F bit 0
PTFPE: equ $41 ;I/O port F pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTFPE7: equ 7 ;bit #7
PTFPE6: equ 6 ;bit #6
PTFPE5: equ 5 ;bit #5
PTFPE4: equ 4 ;bit #4
PTFPE3: equ 3 ;bit #3
PTFPE2: equ 2 ;bit #2
PTFPE1: equ 1 ;bit #1
PTFPE0: equ 0 ;bit #0
; bit position masks
mPTFPE7: equ %10000000 ;port F bit 7
mPTFPE6: equ %01000000 ;port F bit 6
mPTFPE5: equ %00100000 ;port F bit 5
mPTFPE4: equ %00010000 ;port F bit 4
mPTFPE3: equ %00001000 ;port F bit 3
mPTFPE2: equ %00000100 ;port F bit 2
mPTFPE1: equ %00000010 ;port F bit 1
mPTFPE0: equ %00000001 ;port F bit 0
PTFSE: equ $42 ;I/O port F slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTFSE7: equ 7 ;bit #7
PTFSE6: equ 6 ;bit #6
PTFSE5: equ 5 ;bit #5
PTFSE4: equ 4 ;bit #4
PTFSE3: equ 3 ;bit #3
PTFSE2: equ 2 ;bit #2
PTFSE1: equ 1 ;bit #1
PTFSE0: equ 0 ;bit #0
; bit position masks
mPTFSE7: equ %10000000 ;port F bit 7
mPTFSE6: equ %01000000 ;port F bit 6
mPTFSE5: equ %00100000 ;port F bit 5
mPTFSE4: equ %00010000 ;port F bit 4
mPTFSE3: equ %00001000 ;port F bit 3
mPTFSE2: equ %00000100 ;port F bit 2
mPTFSE1: equ %00000010 ;port F bit 1
mPTFSE0: equ %00000001 ;port F bit 0
PTFDD: equ $43 ;I/O port F data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTFDD7: equ 7 ;bit #7
PTFDD6: equ 6 ;bit #6
PTFDD5: equ 5 ;bit #5
PTFDD4: equ 4 ;bit #4
PTFDD3: equ 3 ;bit #3
PTFDD2: equ 2 ;bit #2
PTFDD1: equ 1 ;bit #1
PTFDD0: equ 0 ;bit #0
; bit position masks
mPTFDD7: equ %10000000 ;port F bit 7
mPTFDD6: equ %01000000 ;port F bit 6
mPTFDD5: equ %00100000 ;port F bit 5
mPTFDD4: equ %00010000 ;port F bit 4
mPTFDD3: equ %00001000 ;port F bit 3
mPTFDD2: equ %00000100 ;port F bit 2
mPTFDD1: equ %00000010 ;port F bit 1
mPTFDD0: equ %00000001 ;port F bit 0
PTGD: equ $44 ;I/O port G data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTGD7: equ 7 ;bit #7
PTGD6: equ 6 ;bit #6
PTGD5: equ 5 ;bit #5
PTGD4: equ 4 ;bit #4
PTGD3: equ 3 ;bit #3
PTGD2: equ 2 ;bit #2
PTGD1: equ 1 ;bit #1
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