📄 9s08gb60.inc
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;*********************************************************************
; HEADER_START
;
; $File Name: 9S08GB60.inc$
; Project: Developper's HC08 Bootloader Slave
; Description: S08GB/GT header file
; Platform: HCS08
; $Version: 6.0.3.0$
; $Date: Nov-3-2004$
; $Last Modified By: r30323$
; Company: Freescale Semiconductor
; Security: General Business
;
; ===================================================================
; Copyright (c): Freescale Semiconductor, 2004, All rights reserved.
;
; ===================================================================
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END
;* Author: Jim Sibigtroth - Freescale TSPG
;*
;* Description: Register and bit name definitions for 9S08GB60
;*
;* Documentation: 9S08GB60 family Data Sheet for register and bit explanations
;* HCS08 Family Reference Manual (HCS08RM1/D) appendix B for explanation of equate files
;*
;* Include Files: none
;*
;* Assembler: Metrowerks Code Warrior 3.0 (pre-release)
;* or P&E Microcomputer Systems - CASMS08 (beta v4.02)
;*
;* Revision History: not yet released
;* Rev # Date Who Comments
;* ----- ----------- ------ --------------------------------------------
;* 1.3 28-Apr-03 J-Sib SPCO->SPC0, IIAS->IAAS, AN2111 format
;* 1.2 24-Apr-03 J-Sib correct minor typos in comments
;* 1.1 21-Apr-03 J-Sib comments and modify for CW 3.0 project
;* 1.0 15-Apr-03 J-Sib Release version for 9S09GB60
;********************************************************************************************
;**** Memory Map and Interrupt Vectors ****************************************************
;*
RomStart: equ $1080 ;start of 60K flash
HighRegs: equ $1800 ;start of high page registers
Rom1Start: equ $182C ;start of flash after high regs
RomLast: equ $FFFF ;last flash location
RamStart: equ $0080 ;start of 4096 byte RAM
RamLast: equ $107F ;last RAM location
;
Vrti: equ $FFCC ;RTI (periodic interrupt) vector
Viic: equ $FFCE ;IIC vector
Vatd: equ $FFD0 ;analog to digital conversion vector
Vkeyboard: equ $FFD2 ;keyboard vector
Vsci2tx: equ $FFD4 ;SCI2 transmit vector
Vsci2rx: equ $FFD6 ;SCI2 receive vector
Vsci2err: equ $FFD8 ;SCI2 error vector
Vsci1tx: equ $FFDA ;SCI1 transmit vector
Vsci1rx: equ $FFDC ;SCI1 receive vector
Vsci1err: equ $FFDE ;SCI1 error vector
Vspi: equ $FFE0 ;SPI vector
Vtpm2ovf: equ $FFE2 ;TPM2 overflow vector
Vtpm2ch4: equ $FFE4 ;TPM2 channel 4 vector
Vtpm2ch3: equ $FFE6 ;TPM2 channel 3 vector
Vtpm2ch2: equ $FFE8 ;TPM2 channel 2 vector
Vtpm2ch1: equ $FFEA ;TPM2 channel 1 vector
Vtpm2ch0: equ $FFEC ;TPM2 channel 0 vector
Vtpm1ovf: equ $FFEE ;TPM1 overflow vector
Vtpm1ch2: equ $FFF0 ;TPM1 channel 2 vector
Vtpm1ch1: equ $FFF2 ;TPM1 channel 1 vector
Vtpm1ch0: equ $FFF4 ;TPM1 channel 0 vector
Vicg: equ $FFF6 ;ICG vector
Vlvd: equ $FFF8 ;low voltage detect vector
Virq: equ $FFFA ;IRQ pin vector
Vswi: equ $FFFC ;SWI vector
Vreset: equ $FFFE ;reset vector
;**** Input/Output (I/O) Ports ************************************************************
;*
PTAD: equ $00 ;I/O port A data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTAD7: equ 7 ;bit #7
PTAD6: equ 6 ;bit #6
PTAD5: equ 5 ;bit #5
PTAD4: equ 4 ;bit #4
PTAD3: equ 3 ;bit #3
PTAD2: equ 2 ;bit #2
PTAD1: equ 1 ;bit #1
PTAD0: equ 0 ;bit #0
; bit position masks
mPTAD7: equ %10000000 ;port A bit 7
mPTAD6: equ %01000000 ;port A bit 6
mPTAD5: equ %00100000 ;port A bit 5
mPTAD4: equ %00010000 ;port A bit 4
mPTAD3: equ %00001000 ;port A bit 3
mPTAD2: equ %00000100 ;port A bit 2
mPTAD1: equ %00000010 ;port A bit 1
mPTAD0: equ %00000001 ;port A bit 0
PTAPE: equ $01 ;I/O port A pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTAPE7: equ 7 ;bit #7
PTAPE6: equ 6 ;bit #6
PTAPE5: equ 5 ;bit #5
PTAPE4: equ 4 ;bit #4
PTAPE3: equ 3 ;bit #3
PTAPE2: equ 2 ;bit #2
PTAPE1: equ 1 ;bit #1
PTAPE0: equ 0 ;bit #0
; bit position masks
mPTAPE7: equ %10000000 ;port A bit 7
mPTAPE6: equ %01000000 ;port A bit 6
mPTAPE5: equ %00100000 ;port A bit 5
mPTAPE4: equ %00010000 ;port A bit 4
mPTAPE3: equ %00001000 ;port A bit 3
mPTAPE2: equ %00000100 ;port A bit 2
mPTAPE1: equ %00000010 ;port A bit 1
mPTAPE0: equ %00000001 ;port A bit 0
PTASE: equ $02 ;I/O port A slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTASE7: equ 7 ;bit #7
PTASE6: equ 6 ;bit #6
PTASE5: equ 5 ;bit #5
PTASE4: equ 4 ;bit #4
PTASE3: equ 3 ;bit #3
PTASE2: equ 2 ;bit #2
PTASE1: equ 1 ;bit #1
PTASE0: equ 0 ;bit #0
; bit position masks
mPTASE7: equ %10000000 ;port A bit 7
mPTASE6: equ %01000000 ;port A bit 6
mPTASE5: equ %00100000 ;port A bit 5
mPTASE4: equ %00010000 ;port A bit 4
mPTASE3: equ %00001000 ;port A bit 3
mPTASE2: equ %00000100 ;port A bit 2
mPTASE1: equ %00000010 ;port A bit 1
mPTASE0: equ %00000001 ;port A bit 0
PTADD: equ $03 ;I/O port A data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTADD7: equ 7 ;bit #7
PTADD6: equ 6 ;bit #6
PTADD5: equ 5 ;bit #5
PTADD4: equ 4 ;bit #4
PTADD3: equ 3 ;bit #3
PTADD2: equ 2 ;bit #2
PTADD1: equ 1 ;bit #1
PTADD0: equ 0 ;bit #0
; bit position masks
mPTADD7: equ %10000000 ;port A bit 7
mPTADD6: equ %01000000 ;port A bit 6
mPTADD5: equ %00100000 ;port A bit 5
mPTADD4: equ %00010000 ;port A bit 4
mPTADD3: equ %00001000 ;port A bit 3
mPTADD2: equ %00000100 ;port A bit 2
mPTADD1: equ %00000010 ;port A bit 1
mPTADD0: equ %00000001 ;port A bit 0
PTBD: equ $04 ;I/O port B data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTBD7: equ 7 ;bit #7
PTBD6: equ 6 ;bit #6
PTBD5: equ 5 ;bit #5
PTBD4: equ 4 ;bit #4
PTBD3: equ 3 ;bit #3
PTBD2: equ 2 ;bit #2
PTBD1: equ 1 ;bit #1
PTBD0: equ 0 ;bit #0
; bit position masks
mPTBD7: equ %10000000 ;port B bit 7
mPTBD6: equ %01000000 ;port B bit 6
mPTBD5: equ %00100000 ;port B bit 5
mPTBD4: equ %00010000 ;port B bit 4
mPTBD3: equ %00001000 ;port B bit 3
mPTBD2: equ %00000100 ;port B bit 2
mPTBD1: equ %00000010 ;port B bit 1
mPTBD0: equ %00000001 ;port B bit 0
PTBPE: equ $05 ;I/O port B pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTBPE7: equ 7 ;bit #7
PTBPE6: equ 6 ;bit #6
PTBPE5: equ 5 ;bit #5
PTBPE4: equ 4 ;bit #4
PTBPE3: equ 3 ;bit #3
PTBPE2: equ 2 ;bit #2
PTBPE1: equ 1 ;bit #1
PTBPE0: equ 0 ;bit #0
; bit position masks
mPTBPE7: equ %10000000 ;port B bit 7
mPTBPE6: equ %01000000 ;port B bit 6
mPTBPE5: equ %00100000 ;port B bit 5
mPTBPE4: equ %00010000 ;port B bit 4
mPTBPE3: equ %00001000 ;port B bit 3
mPTBPE2: equ %00000100 ;port B bit 2
mPTBPE1: equ %00000010 ;port B bit 1
mPTBPE0: equ %00000001 ;port B bit 0
PTBSE: equ $06 ;I/O port B slew rate control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTBSE7: equ 7 ;bit #7
PTBSE6: equ 6 ;bit #6
PTBSE5: equ 5 ;bit #5
PTBSE4: equ 4 ;bit #4
PTBSE3: equ 3 ;bit #3
PTBSE2: equ 2 ;bit #2
PTBSE1: equ 1 ;bit #1
PTBSE0: equ 0 ;bit #0
; bit position masks
mPTBSE7: equ %10000000 ;port B bit 7
mPTBSE6: equ %01000000 ;port B bit 6
mPTBSE5: equ %00100000 ;port B bit 5
mPTBSE4: equ %00010000 ;port B bit 4
mPTBSE3: equ %00001000 ;port B bit 3
mPTBSE2: equ %00000100 ;port B bit 2
mPTBSE1: equ %00000010 ;port B bit 1
mPTBSE0: equ %00000001 ;port B bit 0
PTBDD: equ $07 ;I/O port B data direction register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTBDD7: equ 7 ;bit #7
PTBDD6: equ 6 ;bit #6
PTBDD5: equ 5 ;bit #5
PTBDD4: equ 4 ;bit #4
PTBDD3: equ 3 ;bit #3
PTBDD2: equ 2 ;bit #2
PTBDD1: equ 1 ;bit #1
PTBDD0: equ 0 ;bit #0
; bit position masks
mPTBDD7: equ %10000000 ;port B bit 7
mPTBDD6: equ %01000000 ;port B bit 6
mPTBDD5: equ %00100000 ;port B bit 5
mPTBDD4: equ %00010000 ;port B bit 4
mPTBDD3: equ %00001000 ;port B bit 3
mPTBDD2: equ %00000100 ;port B bit 2
mPTBDD1: equ %00000010 ;port B bit 1
mPTBDD0: equ %00000001 ;port B bit 0
PTCD: equ $08 ;I/O port C data register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTCD7: equ 7 ;bit #7
PTCD6: equ 6 ;bit #6
PTCD5: equ 5 ;bit #5
PTCD4: equ 4 ;bit #4
PTCD3: equ 3 ;bit #3
PTCD2: equ 2 ;bit #2
PTCD1: equ 1 ;bit #1
PTCD0: equ 0 ;bit #0
; bit position masks
mPTCD7: equ %10000000 ;port C bit 7
mPTCD6: equ %01000000 ;port C bit 6
mPTCD5: equ %00100000 ;port C bit 5
mPTCD4: equ %00010000 ;port C bit 4
mPTCD3: equ %00001000 ;port C bit 3
mPTCD2: equ %00000100 ;port C bit 2
mPTCD1: equ %00000010 ;port C bit 1
mPTCD0: equ %00000001 ;port C bit 0
PTCPE: equ $09 ;I/O port C pullup enable controls
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
PTCPE7: equ 7 ;bit #7
PTCPE6: equ 6 ;bit #6
PTCPE5: equ 5 ;bit #5
PTCPE4: equ 4 ;bit #4
PTCPE3: equ 3 ;bit #3
PTCPE2: equ 2 ;bit #2
PTCPE1: equ 1 ;bit #1
PTCPE0: equ 0 ;bit #0
; bit position masks
mPTCPE7: equ %10000000 ;port C bit 7
mPTCPE6: equ %01000000 ;port C bit 6
mPTCPE5: equ %00100000 ;port C bit 5
mPTCPE4: equ %00010000 ;port C bit 4
mPTCPE3: equ %00001000 ;port C bit 3
mPTCPE2: equ %00000100 ;port C bit 2
mPTCPE1: equ %00000010 ;port C bit 1
mPTCPE0: equ %00000001 ;port C bit 0
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