📄 slfprg-gz60.asm
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JMP VEC0 ; any of other sources, jump to real application
slfprg:
; CONFIG2 not configured - reset selects SCIBDSRC - SCI clk = BUS clock
MOV #%10010001,CONFIG1 ; COP disable
CLR PCTL
MOV #$02,PCTL ; P = 0, E = 2
MOV #$00,PMSH
MOV #$04,PMSL ; VCO = Xtal * 4 , 32MHz VCO for 8MHz Xtal
MOV #$70,PMRS
BSET 5,PCTL ; TURN ON PLL
BSET 7,PBWC ; PUT IN AUTO BANDWIDTH MODE
LOOP:
BRCLR 6,PBWC,LOOP ; WAIT FOR PLL TO LOCK
BSET 4,PCTL ; SELECT CGMVCLK TO DRIVE CGMOUT
BSET 6,SCC1 ; SCI enable
MOV #%00001100,SCC2 ; transmit & receive enable
MOV #%00110000,SCBR ; 9600Bd @ 8MHz (BUSCLK), /4 /16 /13
LDA SCS1
MOV #ACK,SCDR
LDX #T100MS
L2: CLRA
L1: BRSET 5,SCS1,CAUGHT
DBNZA L1
DBNZX L2
; timeout
ENDPRG_COM:
ILOP ; generate RESET by doing illegal operation
;*******************************************************************************************
CAUGHT: ; CAUGHT IN SELF-PROGRAMMING?
BSR READ
CMPA #ACK
BNE ENDPRG_COM
;*******************************************************************************************
; successful return from all write routines
SUCC:
LDA #ACK
BSR WRITE
;fall thru to background
;*******************************************************************************************
; BEGIN OF BACKGROUND COMMAND LOOP
BCKGND:
BSR READ
CBEQA #ERASE, ERASE_COM ; Erase command
CBEQA #WR_DATA, WR_DATA_COM ; Write (program) command
CBEQA #IDENT, IDENT_COM ; Ident command
IF RCS_ENA = 1
CBEQA #RD_DATA, RD_DATA_COM ; Read command
ENDIF
; if no valid command found (including Quit)
; generate reset too!
ILOP ; generate RESET by doing illegal operation
;*******************************************************************************************
IDENT_COM: ; TRANSFER OF IDENTIFICATION STRING
MOV #ID_STRING1_END-ID_STRING1, LEN
LDHX #ID_STRING1
BSR WRITE_LOOP
BRA BCKGND ; finish without ACK
;*******************************************************************************************
WRITE_LOOP: ; start address in HX, length in LEN
LDA ,X
BSR WRITE
AIX #1
DBNZ LEN, WRITE_LOOP
RTS
;*******************************************************************************************
IF RCS_ENA = 1
RD_DATA_COM:
BSR READ
STA ADRS
BSR READ
STA ADRS+1
BSR READ
STA LEN
LDHX ADRS
BSR WRITE_LOOP
BRA BCKGND ; finish without ACK
ENDIF
;*******************************************************************************************
READ:
BRCLR 5,SCS1,READ
LDA SCDR
RTS
WRITE:
BRCLR 6,SCS1,WRITE
STA SCDR
RTS
;*******************************************************************************************
ERASE_COM:
BSR READ
STA ADRS
BSR READ
STA ADRS+1
LDHX #ERASE_ALG ; LOAD ERASE ALGORITHM TO RAM
STHX SOURCE
MOV #ERASE_ALG_END-ERASE_ALG,STAT
BSR CPY_PRG
BRA PR_N_GO_RAM ; prepare FLCR & FLBPR address in RAM and JUMP to PRG then!
;*******************************************************************************************
WR_DATA_COM:
BSR READ
STA ADRS
BSR READ
STA ADRS+1
BSR READ
STA LEN
STA STAT
LDHX #DAT
WR_DATA_L1:
BSR READ
STA ,X
AIX #1
DBNZ STAT,WR_DATA_L1
; START OF SELF-PROGRAMMING
WR_BUF:
LDHX #WR_ALG ; LOAD WRITE ALGORITHM TO RAM
STHX SOURCE
MOV #WR_ALG_END-WR_ALG,STAT
BSR CPY_PRG
TSX
STHX STACK ; copy stack for later re-call
BRA PR_N_GO_RAM ; prepare FLCR & FLBPR address in RAM and JUMP to PRG then!
RETWR:
LDHX STACK
TXS ; restore stack
JMP SUCC
;*******************************************************************************************
PR_N_GO_RAM:
LDHX #$8000
CPHX ADRS ; FLASH1/FLASH2 boundary at $8000
BHI FL2SEL ; carry set, if 8000 < ADRS (ie. FLASH1, hi)
LDHX #FL1CR
STHX RFLCR
LDHX #FL1BPR
BRA GORAM
FL2SEL:
LDHX #FL2CR
STHX RFLCR
LDHX #FL2BPR
GORAM:
STHX RFLBPR
JMP PRG ; jump to RAM program
;*******************************************************************************************
CPY_PRG:
TSX
STHX STACK ; copy stack for later re-call
LDHX SOURCE ; LOAD WRITE ALGORITHM TO RAM
TXS
LDHX #PRG
CPY_PRG_L1:
PULA
STA ,X
AIX #1
DBNZ STAT,CPY_PRG_L1
LDHX STACK
TXS ; restore stack
RTS
;*******************************************************************************************
ERASE_ALG:
LDA #%00000010
LDHX RFLCR
STA ,X ; ERASE bit on
LDHX RFLBPR
LDA ,X ; dummy read FLBPR
LDHX ADRS ; write anything
STA ,X ; to desired range
D_US #T10US ; wait 10us (tNVS)
LDA #%00001010
LDHX RFLCR
STA ,X ; ERASE bit on, HVEN bit on
D_MS #T1MS ; wait 1ms (tERASE), modifies X!
LDA #%00001000
LDHX RFLCR
STA ,X ; ERASE bit off, HVEN bit still on
D_US #T5US ; wait 5us (tNVH)
STA ,X ; all bits off
D_US #T1US ; wait 1us (tRCV)
JMP SUCC ; finish with ACK
ERASE_ALG_END:
;*******************************************************************************************
WR_ALG:
LDA #%00000001
LDHX RFLCR
STA ,X ; PGM bit on
LDHX RFLBPR
LDA ,X ; dummy read FLBPR
LDHX ADRS ; prepare address
STA ,X ; and write to desired range
D_US #T10US ; wait 10us (tNVS)
LDA #%00001001
LDHX RFLCR
STA ,X ; PGM bit on, HVEN bit on
D_US #T5US ; wait 5us (tPGS)
LDHX #DAT ; prepare data
TXS
LDHX ADRS
MOV LEN,POM
WR_ALG_L1:
PULA
STA ,X
AIX #1
D_US #T30US ; wait 30us (tPROG)
DBNZ POM,WR_ALG_L1 ; copy desired block of data
LDA #%00001000
LDHX RFLCR
STA ,X ; PGM bit off, HVEN bit still on
D_US #T5US ; wait 5us (tNVH)
STA ,X ; HVEN bit off
D_US #T1US ; wait 1us (tRCV)
JMP RETWR ; finish with ACK (& restore STACK before)
WR_ALG_END:
;*******************************************************************************************
END
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