example_281xgpiotoggle.c

tms320f2812 GPIO 试验及FFT,FIR

//###########################################################################
//
// FILE:    Example_281xGpioToggle.c
//
// TITLE:   DSP281x Device GPIO toggle test program. 
//
// ASSUMPTIONS:
//
//          This program requires the DSP281x V1.00 header files.  
//          As supplied, this project is configured for "boot to H0" operation. 
//
//          Other then boot mode pin configuration, no other hardware configuration
//          is required.
//
//          Three different examples are included. Select the example 
//          (data, set/clear or toggle) to execute before compiling using
//          the #define statements found at the top of the code.   
//
// DESCRIPTION:
//
//          Toggle all of the GPIO PORT pins 
//        
//          The pins can be observed using Oscilloscope.  
// 
//
//###########################################################################
//
// Original by S.S.
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
// 1.00 | 11 Sep 2003 | L.H. | First Release
//###########################################################################

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File
#include <fft.h>

// Select the example to compile in.  Only one example should be set as 1
// the rest should be set as 0.
#define EXAMPLE1 0  // Use DATA registers to toggle I/O's
#define EXAMPLE2 0  // Use SET/CLEAR registers to toggle I/O's
#define EXAMPLE3 0  // Use TOGGLE registers to toggle I/O's

#pragma DATA_SECTION(mytest, "TEST");
long mytest[100];

#pragma DATA_SECTION(ipcb, "FFTipcb");
long ipcb[1024+2];
RFFT32  fft=RFFT32_1024P_DEFAULTS;

void Initzone2(void)
{

    XintfRegs.XINTCNF2.bit.XTIMCLK = 0; //old is 1
    // No write buffering
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK/2 
    XintfRegs.XINTCNF2.bit.CLKMODE = 0; //old is 1
    

    XintfRegs.XTIMING2.bit.XWRLEAD = 1;  //old is 3-7-3
    XintfRegs.XTIMING2.bit.XWRACTIVE = 3;
    XintfRegs.XTIMING2.bit.XWRTRAIL = 1;
    // Zone read timing
    XintfRegs.XTIMING2.bit.XRDLEAD = 1; //old is 3-7-3
    XintfRegs.XTIMING2.bit.XRDACTIVE = 3;
    XintfRegs.XTIMING2.bit.XRDTRAIL = 1;
    
    // double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING2.bit.X2TIMING = 0;//old is 1

    // Zone will sample XREADY signal 
    XintfRegs.XTIMING2.bit.USEREADY = 0; //old is 1
    XintfRegs.XTIMING2.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING2.bit.XSIZE = 3;


     // Bank switching
    // Assume Zone 7 is slow, so add additional BCYC cycles 
    // when ever switching from Zone 7 to another Zone.  
    // This will help avoid bus contention.
    XintfRegs.XBANK.bit.BANK = 7;
    XintfRegs.XBANK.bit.BCYC = 7;

   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning.  

   asm(" RPT #7 || NOP"); 
    
    
}

void main(void)
{
	
	unsigned int i;
	int j;
   
   InitSysCtrl();
   DINT;

   //InitPieCtrl();


   IER = 0x0000;
   IFR = 0x0000;

   //InitPieVectTable();
   Initzone2();
   j=0;
   mytest[0]=10;
   //InitXintf();
   j=0;
   mytest[1]=11;
   //InitXintf();
   j=0;
   mytest[2]=12;
  for(j=0;j<100;j++)
   {
   
   		mytest[j]=j*65536;
   		
   	}
  // asm("nop");
  i=0;
  i=1;
  i=2;
   for(i=0;i<1024;i++)
		{
		ipcb[i]=i*65536;	
		}
	
		fft.ipcbptr=ipcb;
        fft.magptr=ipcb;  
        //fft.winptr=(long *)win;
        fft.init(&fft);  

		RFFT32_brev(ipcb,ipcb,1024);  // Input after windowing 
        fft.calc(&fft);
        fft.split(&fft);
        fft.mag(&fft); 
		
while(1);	

}