📄 intel奔腾系列cpu指令全集(包含p4).htm
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D9 FB FSINCOS Compute the sine and cosine of ST(0);
REPlace ST(0) with the sine, and push the cosine
onto the register stack.
D9 FA FSQRT Computes square root of ST(0) and
stores the result in ST(0)
D9 /2 FST m32fp Copy ST(0) to m32fp
DD /2 FST m64fp Copy ST(0) to m64fp
DD D0+i FST ST(i) Copy ST(0) to ST(i)
D9 /3 FSTP m32fp Copy ST(0) to m32fp and pop register stack
DD /3 FSTP m64fp Copy ST(0) to m64fp and pop register stack
DB /7 FSTP m80fp Copy ST(0) to m80fp and pop register stack
DD D8+i FSTP ST(i) Copy ST(0) to ST(i) and pop register stack
9B D9 /7 FSTCW m2byte Store FPU control word to m2byte after checking for
pending unmasked floating-point exceptions.
D9 /7 FNSTCW* m2byte Store FPU control word to m2byte without checking for
pending unmasked floating-point exceptions.
9B D9 /6 FSTENV m14/28byte Store FPU environment to m14byte or m28byte after
checking for pending unmasked floating-point
exceptions. Then mask all floating-point exceptions.
D9 /6 FNSTENV* m14/28byte Store FPU environment to m14byte or m28byte without
checking for pending unmasked floating-point
exceptions. Then mask all floating-point exceptions.
9B DD /7 FSTSW m2byte Store FPU status word at m2byte after checking for
pending unmasked floating-point exceptions.
9B DF E0 FSTSW AX Store FPU status word in AX register after checking
for pending unmasked floating-point exceptions.
DD /7 FNSTSW* m2byte Store FPU status word at m2byte without checking for
pending unmasked floating-point exceptions.
DF E0 FNSTSW* AX Store FPU status word in AX register without checking
for pending unmasked floating-point exceptions.
D8 /4 FSUB m32fp Subtract m32fp from ST(0) and store result in ST(0)
DC /4 FSUB m64fp Subtract m64fp from ST(0) and store result in ST(0)
D8 E0+i FSUB ST(0), ST(i) Subtract ST(i) from ST(0) and store result in ST(0)
DC E8+i FSUB ST(i), ST(0) Subtract ST(0) from ST(i) and store result in ST(i)
DE E8+i FSUBP ST(i), ST(0) Subtract ST(0) from ST(i), store result in ST(i),
and pop register stack
DE E9 FSUBP Subtract ST(0) from ST(1), store result in ST(1),
and pop register stack
DA /4 FISUB m32int Subtract m32int from ST(0) and store result in ST(0)
DE /4 FISUB m16int Subtract m16int from ST(0) and store result in ST(0)
D8 /5 FSUBR m32fp Subtract ST(0) from m32fp and store result in ST(0)
DC /5 FSUBR m64fp Subtract ST(0) from m64fp and store result in ST(0)
D8 E8+i FSUBR ST(0), ST(i) Subtract ST(0) from ST(i) and store result in ST(0)
DC E0+i FSUBR ST(i), ST(0) Subtract ST(i) from ST(0) and store result in ST(i)
DE E0+i FSUBRP ST(i), ST(0) Subtract ST(i) from ST(0), store result in ST(i),
and pop register stack
DE E1 FSUBRP Subtract ST(1) from ST(0), store result in ST(1),
and pop register stack
DA /5 FISUBR m32int Subtract ST(0) from m32int and store result in ST(0)
DE /5 FISUBR m16int Subtract ST(0) from m16int and store result in ST(0)
D9 E4 FTST Compare ST(0) with 0.0.
DD E0+i FUCOM ST(i) Compare ST(0) with ST(i)
DD E1 FUCOM Compare ST(0) with ST(1)
DD E8+i FUCOMP ST(i) Compare ST(0) with ST(i) and pop register stack
DD E9 FUCOMP Compare ST(0) with ST(1) and pop register stack
DA E9 FUCOMPP Compare ST(0) with ST(1) and pop register stack twice
D9 E5 FXAM Classify value or number in ST(0)
D9 C8+i FXCH ST(i) Exchange the contents of ST(0) and ST(i)
D9 C9 FXCH Exchange the contents of ST(0) and ST(1)
0F AE /1 FXRSTOR m512byte Restore the x87 FPU, MMX, XMM, and MXCSR register
state from m512byte.
0F AE /0 FXSAVE m512byte Save the x87 FPU, MMX, XMM, and MXCSR register
state to m512byte.
D9 F4 FXTRACT Separate value in ST(0) into exponent and significand,
store exponent in ST(0), and push the significand
onto the register stack.
D9 F1 FYL2X REPlace ST(1) with (ST(1)*log2ST(0)) and
pop the register stack
D9 F9 FYL2XP1 REPlace ST(1) with ST(1)*log2(ST(0) + 1.0) and
pop the register stack
F4 HLT Halt
F6 /7 IDIV r/m8 Signed divide AX by r/m8, with result stored in
AL ←Quotient, AH ←Remainder
F7 /7 IDIV r/m16 Signed divide DX:AX by r/m16, with result stored in
AX ←Quotient, DX ←Remainder
F7 /7 IDIV r/m32 Signed divide EDX:EAX by r/m32, with result stored in
EAX ←Quotient, EDX ←Remainder
F6 /5 IMUL r/m8 AX ← AL*r/m byte
F7 /5 IMUL r/m16 DX:AX ←AX*r/m word
F7 /5 IMUL r/m32 EDX:EAX ←EAX*r/m doubleword
0F AF /r IMUL r16,r/m16 word register ←word register*r/m word
0F AF /r IMUL r32,r/m32 doubleword register ←doubleword register*r/m
doubleword
6B /r ib IMUL r16,r/m16,imm8 word register ←r/m16*sign-extended immediate byte
6B /r ib IMUL r32,r/m32,imm8 doubleword register ←r/m32*sign-extended
immediate byte
6B /r ib IMUL r16,imm8 word register ←word register*sign-extended
immediate byte
6B /r ib IMUL r32,imm8 doubleword register ←doubleword register
*sign-extended immediate byte
69 /r iw IMUL r16,r/m16,imm16 word register ←r/m16*immediate word
69 /r id IMUL r32,r/m32,imm32 doubleword register ←r/m32*immediate doubleword
69 /r iw IMUL r16,imm16 word register ←r/m16*immediate word
E4 ib IN AL,imm8 Input byte from imm8 I/O port address into AL
E5 ib IN AX,imm8 Input byte from imm8 I/O port address into AX
E5 ib IN EAX,imm8 Input byte from imm8 I/O port address into EAX
EC IN AL,DX Input byte from I/O port in DX into AL
ED IN AX,DX Input word from I/O port in DX into AX
ED IN EAX,DX Input doubleword from I/O port in DX into EAX
FE /0 INC r/m8 Increment r/m byte by 1
FF /0 INC r/m16 Increment r/m word by 1
FF /0 INC r/m32 Increment r/m doubleword by 1
40+ rw INC r16 Increment word register by 1
40+ rd INC r32 Increment doubleword register by 1
6C INS m8, DX Input byte from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m16, DX Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m32, DX Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI
6C INSB Input byte from I/O port specified in DX into memory
location specified with ES:(E)DI
6D INSW Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INSD Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI
CC INT 3 Interrupt 3— trap to debugger
CD ib INT imm8 Interrupt vector number specified by immediate byte
CE INTO Interrupt 4— if overflow flag is 1
0F 08 INVD Flush internal caches; initiate flushing of
external caches.
0F 01/7 INVLPG m Invalidate TLB Entry for page that contains m
CF IRET Interrupt return (16-bit operand size)
CF IRETD Interrupt return (32-bit operand size)
77 cb JA rel8 Jump short if above (CF=0 and ZF=0)
73 cb JAE rel8 Jump short if above or equal (CF=0)
72 cb JB rel8 Jump short if below (CF=1)
76 cb JBE rel8 Jump short if below or equal (CF=1 or ZF=1)
72 cb JC rel8 Jump short if carry (CF=1)
E3 cb JCXZ rel8 Jump short if CX register is 0
E3 cb JECXZ rel8 Jump short if ECX register is 0
74 cb JE rel8 Jump short if equal (ZF=1)
7F cb JG rel8 Jump short if greater (ZF=0 and SF=OF)
7D cb JGE rel8 Jump short if greater or equal (SF=OF)
7C cb JL rel8 Jump short if less (SF<>OF)
7E cb JLE rel8 Jump short if less or equal (ZF=1 or SF<>OF)
76 cb JNA rel8 Jump short if not above (CF=1 or ZF=1)
72 cb JNAE rel8 Jump short if not above or equal (CF=1)
73 cb JNB rel8 Jump short if not below (CF=0)
77 cb JNBE rel8 Jump short if not below or equal (CF=0 and ZF=0)
73 cb JNC rel8 Jump short if not carry (CF=0)
75 cb JNE rel8 Jump short if not equal (ZF=0)
7E cb JNG rel8 Jump short if not greater (ZF=1 or SF<>OF)
7C cb JNGE rel8 Jump short if not greater or equal (SF<>OF)
7D cb JNL rel8 Jump short if not less (SF=OF)
7F cb JNLE rel8 Jump short if not less or equal (ZF=0 and SF=OF)
71 cb JNO rel8 Jump short if not overflow (OF=0)
7B cb JNP rel8 Jump short if not parity (PF=0)
79 cb JNS rel8 Jump short if not sign (SF=0)
75 cb JNZ rel8 Jump short if not zero (ZF=0)
70 cb JO rel8 Jump short if overflow (OF=1)
7A cb JP rel8 Jump short if parity (PF=1)
7A cb JPE rel8 Jump short if parity even (PF=1)
7B cb JPO rel8 Jump short if parity odd (PF=0)
78 cb JS rel8 Jump short if sign (SF=1)
74 cb JZ rel8 Jump short if zero (ZF =1)
0F 87 cw/cd JA rel16/32 Jump near if above (CF=0 and ZF=0)
0F 83 cw/cd JAE rel16/32 Jump near if above or equal (CF=0)
0F 82 cw/cd JB rel16/32 Jump near if below (CF=1)
0F 86 cw/cd JBE rel16/32 Jump near if below or equal (CF=1 or ZF=1)
0F 82 cw/cd JC rel16/32 Jump near if carry (CF=1)
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)
0F 8F cw/cd JG rel16/32 Jump near if greater (ZF=0 and SF=OF)
0F 8D cw/cd JGE rel16/32 Jump near if greater or equal (SF=OF)
0F 8C cw/cd JL rel16/32 Jump near if less (SF<>OF)
0F 8E cw/cd JLE rel16/32 Jump near if less or equal (ZF=1 or SF<>OF)
0F 86 cw/cd JNA rel16/32 Jump near if not above (CF=1 or ZF=1)
0F 82 cw/cd JNAE rel16/32 Jump near if not above or equal (CF=1)
0F 83 cw/cd JNB rel16/32 Jump near if not below (CF=0)
0F 87 cw/cd JNBE rel16/32 Jump near if not below or equal (CF=0 and ZF=0)
0F 83 cw/cd JNC rel16/32 Jump near if not carry (CF=0)
0F 85 cw/cd JNE rel16/32 Jump near if not equal (ZF=0)
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