📄 intel奔腾系列cpu指令全集(包含p4).htm
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<center class="p12"><font color="red"><b>Intel奔腾系列CPU指令全集(包含P4)</b></font></center><br>
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作者 ：ddcrack (2002/03/05)<br>
笨冬瓜 ：<a href="http://ddcrack.yeah.net/">ddcrack.yeah.net</a>
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资料来源：<font color="red" class="p12"><b>IA-32 Intel Architecture Software Developer Manual Volume 2 : Instruction Set Reference</b></font><br>
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<pre><b><hr size="2" width="100%">
<font color="green">机器码 指令代码 说明</font></b>
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37 AAA ASCII adjust AL after addition
D5 0A AAD ASCII adjust AX before division
D5 ib (No mnemonic) Adjust AX before division to number base imm8
D4 0A AAM ASCII adjust AX after multiply
D4 ib (No mnemonic) Adjust AX after multiply to number base imm8
3F AAS ASCII adjust AL after subtraction
14 ib ADC AL,imm8 Add with carry imm8 to AL
15 iw ADC AX,imm16 Add with carry imm16 to AX
15 id ADC EAX,imm32 Add with carry imm32 to EAX
80 /2 ib ADC r/m8,imm8 Add with carry imm8 to r/m8
81 /2 iw ADC r/m16,imm16 Add with carry imm16 to r/m16
81 /2 id ADC r/m32,imm32 Add with CF imm32 to r/m32
83 /2 ib ADC r/m16,imm8 Add with CF sign-extended imm8 to r/m16
83 /2 ib ADC r/m32,imm8 Add with CF sign-extended imm8 into r/m32
10 /r ADC r/m8,r8 Add with carry byte register to r/m8
11 /r ADC r/m16,r16 Add with carry r16 to r/m16
11 /r ADC r/m32,r32 Add with CF r32 to r/m32
12 /r ADC r8,r/m8 Add with carry r/m8 to byte register
13 /r ADC r16,r/m16 Add with carry r/m16 to r16
13 /r ADC r32,r/m32 Add with CF r/m32 to r32
04 ib ADD AL,imm8 Add imm8 to AL
05 iw ADD AX,imm16 Add imm16 to AX
05 id ADD EAX,imm32 Add imm32 to EAX
80 /0 ib ADD r/m8,imm8 Add imm8 to r/m8
81 /0 iw ADD r/m16,imm16 Add imm16 to r/m16
81 /0 id ADD r/m32,imm32 Add imm32 to r/m32
83 /0 ib ADD r/m16,imm8 Add sign-extended imm8 to r/m16
83 /0 ib ADD r/m32,imm8 Add sign-extended imm8 to r/m32
00 /r ADD r/m8,r8 Add r8 to r/m8
01 /r ADD r/m16,r16 Add r16 to r/m16
01 /r ADD r/m32,r32 Add r32 to r/m32
02 /r ADD r8,r/m8 Add r/m8 to r8
03 /r ADD r16,r/m16 Add r/m16 to r16
03 /r ADD r32,r/m32 Add r/m32 to r32
66 0F 58 /r ADDPD xmm1, xmm2/m128 Add packed double-precision floating-point values
from xmm2/m128 to xmm1.
0F 58 /r ADDPS xmm1, xmm2/m128 Add packed single-precision floating-point values
from xmm2/m128 to xmm1.
F2 0F 58 /r ADDSD xmm1, xmm2/m64 Add the low double-precision floating-point value
from xmm2/m64 to xmm1.
F3 0F 58 /r ADDSS xmm1, xmm2/m32 Add the low single-precision floating-point value
from xmm2/m32 to xmm1.
24 ib AND AL,imm8 AL AND imm8
25 iw AND AX,imm16 AX AND imm16
25 id AND EAX,imm32 EAX AND imm32
80 /4 ib AND r/m8,imm8 r/m8 AND imm8
81 /4 iw AND r/m16,imm16 r/m16 AND imm16
81 /4 id AND r/m32,imm32 r/m32 AND imm32
83 /4 ib AND r/m16,imm8 r/m16 AND imm8 (sign-extended)
83 /4 ib AND r/m32,imm8 r/m32 AND imm8 (sign-extended)
20 /r AND r/m8,r8 r/m8 AND r8
21 /r AND r/m16,r16 r/m16 AND r16
21 /r AND r/m32,r32 r/m32 AND r32
22 /r AND r8,r/m8 r8 AND r/m8
23 /r AND r16,r/m16 r16 AND r/m16
23 /r AND r32,r/m32 r32 AND r/m32
66 0F 54 /r ANDPD xmm1, xmm2/m128 Bitwise logical AND of xmm2/m128 and xmm1.
0F 54 /r ANDPS xmm1, xmm2/m128 Bitwise logical AND of xmm2/m128 and xmm1.
66 0F 55 /r ANDNPD xmm1, xmm2/m128 Bitwise logical AND NOT of xmm2/m128 and xmm1.
0F 55 /r ANDNPS xmm1, xmm2/m128 Bitwise logical AND NOT of xmm2/m128 and xmm1.
63 /r ARPL r/m16,r16 Adjust RPL of r/m16 to not less than RPL of r16
62 /r BOUND r16, m16&16 Check if r16 (array index) is within bounds
specified by m16&16
62 /r BOUND r32, m32&32 Check if r32 (array index) is within bounds
specified by m16&16
0F BC BSF r16,r/m16 Bit scan forward on r/m16
0F BC BSF r32,r/m32 Bit scan forward on r/m32
0F BD BSR r16,r/m16 Bit scan reverse on r/m16
0F BD BSR r32,r/m32 Bit scan reverse on r/m32
0F C8+rd BSWAP r32 Reverses the byte order of a 32-bit register.
0F A3 BT r/m16,r16 Store selected bit in CF flag
0F A3 BT r/m32,r32 Store selected bit in CF flag
0F BA /4 ib BT r/m16,imm8 Store selected bit in CF flag
0F BA /4 ib BT r/m32,imm8 Store selected bit in CF flag
0F BB BTC r/m16,r16 Store selected bit in CF flag and complement
0F BB BTC r/m32,r32 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m16,imm8 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m32,imm8 Store selected bit in CF flag and complement
0F B3 BTR r/m16,r16 Store selected bit in CF flag and clear
0F B3 BTR r/m32,r32 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m16,imm8 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m32,imm8 Store selected bit in CF flag and clear
0F AB BTS r/m16,r16 Store selected bit in CF flag and set
0F AB BTS r/m32,r32 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m16,imm8 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m32,imm8 Store selected bit in CF flag and set
E8 cw CALL rel16 Call near, relative, displacement relative to
next instruction
E8 cd CALL rel32 Call near, relative, displacement relative to
next instruction
FF /2 CALL r/m16 Call near, absolute indirect, address given in r/m16
FF /2 CALL r/m32 Call near, absolute indirect, address given in r/m32
9A cd CALL ptr16:16 Call far, absolute, address given in operand
9A cp CALL ptr16:32 Call far, absolute, address given in operand
FF /3 CALL m16:16 Call far, absolute indirect, address given in m16:16
FF /3 CALL m16:32 Call far, absolute indirect, address given in m16:32
98 cb W AX ←sign-extend of AL
98 CWDE EAX ←sign-extend of AX
F8 CLC Clear CF flag
FC CLD Clear DF flag
0F AE /7 CLFLUSH m8 Flushes cache line containing m8.
FA CLI Clear interrupt flag; interrupts disabled when
interrupt flag cleared
0F 06 CLTS Clears TS flag in CR0
F5 CMC Complement CF flag
0F 47 /r CMOVA r16, r/m16 Move if above (CF=0 and ZF=0)
0F 47 /r CMOVA r32, r/m32 Move if above (CF=0 and ZF=0)
0F 43 /r CMOVAE r16, r/m16 Move if above or equal (CF=0)
0F 43 /r CMOVAE r32, r/m32 Move if above or equal (CF=0)
0F 42 /r CMOVB r16, r/m16 Move if below (CF=1)
0F 42 /r CMOVB r32, r/m32 Move if below (CF=1)
0F 46 /r CMOVBE r16, r/m16 Move if below or equal (CF=1 or ZF=1)
0F 46 /r CMOVBE r32, r/m32 Move if below or equal (CF=1 or ZF=1)
0F 42 /r CMOVC r16, r/m16 Move if carry (CF=1)
0F 42 /r CMOVC r32, r/m32 Move if carry (CF=1)
0F 44 /r CMOVE r16, r/m16 Move if equal (ZF=1)
0F 44 /r CMOVE r32, r/m32 Move if equal (ZF=1)
0F 4F /r CMOVG r16, r/m16 Move if greater (ZF=0 and SF=OF)
0F 4F /r CMOVG r32, r/m32 Move if greater (ZF=0 and SF=OF)
0F 4D /r CMOVGE r16, r/m16 Move if greater or equal (SF=OF)
0F 4D /r CMOVGE r32, r/m32 Move if greater or equal (SF=OF)
0F 4C /r CMOVL r16, r/m16 Move if less (SF<>OF)
0F 4C /r CMOVL r32, r/m32 Move if less (SF<>OF)
0F 4E /r CMOVLE r16, r/m16 Move if less or equal (ZF=1 or SF<>OF)
0F 4E /r CMOVLE r32, r/m32 Move if less or equal (ZF=1 or SF<>OF)
0F 46 /r CMOVNA r16, r/m16 Move if not above (CF=1 or ZF=1)
0F 46 /r CMOVNA r32, r/m32 Move if not above (CF=1 or ZF=1)
0F 42 /r CMOVNAE r16, r/m16 Move if not above or equal (CF=1)
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