📄 top_pci32.map.rpt
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Analysis & Synthesis report for top_pci32
Wed Apr 06 12:55:19 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed Apr 06 12:55:19 2005 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; top_pci32 ;
; Top-level Entity Name ; top_pci32 ;
; Family ; MAX II ;
+-----------------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM1270F256C5ES ; ;
; Family name ; MAX II ; Stratix ;
; Use smart compilation ; Normal ; Normal ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; top_pci32 ; top_pci32 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Enable M512 Memory Blocks ; On ; On ;
+--------------------------------------------------------------------+-----------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------------------------------+
; local/top_local.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/top_local.v ;
; local/lcd_cntrl.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/lcd_cntrl.v ;
; local/mem_cntrl.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/mem_cntrl.v ;
; local/perip.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/perip.v ;
; local/temp_cntrl.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/temp_cntrl.v ;
; top_pci32.v ; yes ; E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Apr 06 12:55:16 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top_pci32 -c top_pci32
Info: Found 1 design units, including 1 entities, in source file local/top_local.v
Info: Found entity 1: top_local
Info: Found 1 design units, including 1 entities, in source file local/lcd_cntrl.v
Info: Found entity 1: lcd_cntrl
Info: Found 1 design units, including 1 entities, in source file local/mem_cntrl.v
Info: Found entity 1: mem_cntrl
Info: Found 1 design units, including 1 entities, in source file local/perip.v
Info: Found entity 1: perip
Info: Found 1 design units, including 1 entities, in source file local/temp_cntrl.v
Info: Found entity 1: temp_cntrl
Warning: Verilog HDL net warning at top_pci32.v(116): created undeclared net "lt_rdyn"
Warning: Verilog HDL net warning at top_pci32.v(117): created undeclared net "lt_abortn"
Warning: Verilog HDL net warning at top_pci32.v(118): created undeclared net "lt_discn"
Warning: Verilog HDL net warning at top_pci32.v(119): created undeclared net "lirqn"
Warning: Verilog HDL net warning at top_pci32.v(123): created undeclared net "sram_ce2"
Warning: Verilog HDL net warning at top_pci32.v(142): created undeclared net "lt_framen"
Warning: Verilog HDL net warning at top_pci32.v(143): created undeclared net "lt_ackn"
Warning: Verilog HDL net warning at top_pci32.v(144): created undeclared net "lt_dxfrn"
Info: Found 1 design units, including 1 entities, in source file top_pci32.v
Info: Found entity 1: top_pci32
Error: Node instance "core" instantiates undefined entity "t32"
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 8 warnings
Error: Processing ended: Wed Apr 06 12:55:19 2005
Error: Elapsed time: 00:00:05
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