readme.txt

MAXII-PCI接口CORE,MAXII-PCI接口CORE[分享]

This directory has the rtl (Verilog) associated with the MAX II PCI reference design. 
top_pci32.v is the top level of the design. The core directory contains the wizard 
generated files for the 32-bit/33 MHz PCI Target.
The local directory has all the files for local reference design.