head.s

ARM9 的head。BOOTLOAD和串口IO的部分 if.q if

	include config.inc
	;include linkage.inc
	include machine.inc

	EXTERN Main
	EXTERN nand_read_ll
; Start of executable code 
	AREA head,CODE,READONLY
		;ENTRY(_start)
		;ENTRY(ResetEntryPoint)
	ENTRY
;
; Exception vector table (physical address = 0x00000000)
;
	GBLL	CONFIG_DEBUG_LL
	GLOBAL ResetEntryPoint
; 0x00: Reset
ResetEntryPoint	b	Reset

; 0x04: Undefined instruction exception
UndefEntryPoint
	b	HandleUndef

; 0x08: Software interrupt exception
SWIEntryPoint
	b	HandleSWI

; 0x0c: Prefetch Abort (Instruction Fetch Memory Abort)
PrefetchAbortEnteryPoint
	b	HandlePrefetchAbort

; 0x10: Data Access Memory Abort
DataAbortEntryPoint
	b	HandleDataAbort

; 0x14: Not used
NotUsedEntryPoint
	b	HandleNotUsed

; 0x18: IRQ(Interrupt Request) exception
IRQEntryPoint
	b	HandleIRQ

; 0x1c: FIQ(Fast Interrupt Request) exception
FIQEntryPoint
	b	HandleFIQ

;
; VIVI magics
;

; 0x20: magic number so we can verify that we only put 
	    DCD   0
; 0x24:
	    DCD   0
; 0x28: where this vivi was linked, so we can put it in memory in the right place
	    DCD   ResetEntryPoint
; 0x2C: this contains the platform, cpu and machine id
	    DCD   ARCHITECTURE_MAGIC
; 0x30: vivi capabilities 
	    DCD   0
	[ :DEF: CONFIG_PM
; 0x34:
	b	SleepRamProc
	]
	[ :DEF: CONFIG_TEST
; 0x38:
	b	hmi
	]


;
; Start VIVI head
;
Reset
	; disable watch dog timer
	mov	r1, #0x53000000
	mov	r2, #0x0
	str	r2, [r1]

	[ :DEF: CONFIG_S3C2410_MPORT3
	mov	r1, #0x56000000
	mov	r2, #0x00000005
	str	r2, [r1, #0x70]
	mov r2, #0x00000001
	str	r2, [r1, #0x78]
	mov	r2, #0x00000001
	str r2, [r1, #0x74]
	]

	; disable all interrupts
	mov	r1, #INT_CTL_BASE
	mov	r2, #0xffffffff
	str	r2, [r1, #oINTMSK]
	ldr	r2, =0x7ff
	str	r2, [r1, #oINTSUBMSK]	

	; initialise system clocks
	mov	r1, #CLK_CTL_BASE
	mvn	r2, #0xff000000
	str	r2, [r1, #oLOCKTIME]

	;ldr	r2, mpll_50mhz
	;str	r2, [r1, #oMPLLCON]
    [ :LNOT::DEF:  CONFIG_S3C2410_MPORT1
	; 1:2:4
	mov	r1, #CLK_CTL_BASE
	mov	r2, #0x3
	str	r2, [r1, #oCLKDIVN]

	mrc	p15, 0, r1, c1, c0, 0		; read ctrl register 
	orr	r1, r1, #0xc0000000		; Asynchronous  
	mcr	p15, 0, r1, c1, c0, 0		; write ctrl register

	; now, CPU clock is 200 Mhz
	mov	r1, #CLK_CTL_BASE
	ldr	r2, mpll_200mhz
	str	r2, [r1, #oMPLLCON]
    |
	; 1:2:2
    mov r1, #CLK_CTL_BASE
    ldr r2, clock_clkdivn
    str r2, [r1, #oCLKDIVN]

    mrc p15, 0, r1, c1, c0, 0       ; read ctrl register
    orr r1, r1, #0xc0000000     ; Asynchronous
    mcr p15, 0, r1, c1, c0, 0       ; write ctrl register

    ; now, CPU clock is 100 Mhz
    mov r1, #CLK_CTL_BASE
    ldr r2, mpll_100mhz
    str r2, [r1, #oMPLLCON]
    ]
	bl	memsetup

    [ :DEF:  CONFIG_PM
	; Check if this is a wake-up from sleep
	ldr	r1, PMST_ADDR
	ldr	r0, [r1]
	tst	r0, #(PMST_SMR)
	bne	WakeupStart
    ]


    [ :DEF:  CONFIG_S3C2410_SMDK
	; All LED on
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F
	ldr	r2,=0x55aa
	str	r2, [r1, #oGPIO_CON]
	mov	r2, #0xff
	str	r2, [r1, #oGPIO_UP]
	mov	r2, #0x00
	str	r2, [r1, #oGPIO_DAT]
    ]

    [  {false}
	; SVC
	mrs	r0, cpsr
	bic	r0, r0, #0xdf
	orr	r1, r0, #0xd3
	msr	cpsr_all, r1
    ]

	; set GPIO for UART
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_H
	ldr	r2, gpio_con_uart	
	str	r2, [r1, #oGPIO_CON]
	ldr	r2, gpio_up_uart
	str	r2, [r1, #oGPIO_UP]	
	bl	InitUART

    [ :DEF:  CONFIG_DEBUG_LL
	; Print current Program Counter
	ldr	r1, SerBase
	mov	r0, #'\r'
	bl	PrintChar
	mov	r0, #'\n'
	bl	PrintChar
	mov	r0, #';'
	bl	PrintChar
	mov	r0, pc
	bl	PrintHexWord
    ]


    [ :DEF:  CONFIG_BOOTUP_MEMTEST
	; simple memory test to find some DRAM flaults.
	bl	memtest
    ]

    [ :DEF:  CONFIG_S3C2410_NAND_BOOT
	bl	copy_myself

	; jump to ram
	ldr	r1, =on_the_ram
	add	pc, r1, #0
	nop
	nop
1	b	%B1		

; infinite loop

on_the_ram
    ]

    [ :DEF:  CONFIG_DEBUG_LL
	ldr	r1, SerBase
	ldr	r0, STR_STACK
	bl	PrintWord
	ldr	r0, DW_STACK_START
	bl	PrintHexWord
    ]

	; get read to call C functions
	ldr	sp, DW_STACK_START	; setup stack pointer
	mov	fp, #0			; no previous frame, so fp=0
	mov	a2, #0			; set argv to NULL 

	bl	Main			; call main 

	mov	pc, #FLASH_BASE		; otherwise, reboot

;
; End VIVI head
;

;
; subroutines
;

;
; Wake-up codes
;
    [ :DEF:  CONFIG_PM
WakeupStart
	; Clear sleep reset bit
	ldr	r0, PMST_ADDR
	mov	r1, #PMST_SMR
	str	r1, [r0]

	; Release the SDRAM signal protections
	ldr	r0, PMCTL1_ADDR
	ldr	r1, [r0]
	bic	r1, r1, #(SCLKE | SCLK1 | SCLK0)
	str	r1, [r0]

	; Go...
	ldr	r0, PMSR0_ADDR	; read a return address
	ldr	r1, [r0]
	mov	pc, r1
	nop
	nop
1	b	%b1		; infinite loop

SleepRamProc
	; SDRAM is in the self-refresh mode */
	ldr	r0, REFR_ADDR
	ldr	r1, [r0]
	orr	r1, r1, #SELF_REFRESH
	str	r1, [r0]

	; wait until SDRAM into self-refresh
	mov	r1, #16
1	subs	r1, r1, #1	
	bne	%b1

	; Set the SDRAM singal protections
	ldr	r0, PMCTL1_ADDR
	ldr	r1, [r0]
	orr	r1, r1, #(SCLKE | SCLK1 | SCLK0)
	str	r1, [r0]

;	 Sleep... Now
	ldr	r0, PMCTL0_ADDR
	ldr	r1, [r0]
	orr	r1, r1, #SLEEP_ON
	str	r1, [r0]	
1	b	%b1

    [ :DEF:  CONFIG_TEST
hmi
	ldr	r0, PMCTL0_ADDR
	ldr	r1, =0x7fff0
	str	r1, [r0]
	
	; All LED on
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F
	ldr	r2,=0x55aa
	str	r2, [r1, #oGPIO_CON]
	mov	r2, #0xff
	str	r2, [r1, #oGPIO_UP]
	mov	r2, #0xe0
	str	r2, [r1, #oGPIO_DAT]
1	b	%b1
    ]

    ]

	GLOBAL memsetup
	; initialise the static memory 

	; set memory control registers
memsetup
	mov	r1, #MEM_CTL_BASE
	adrl	r2, mem_cfg_val
	add	r3, r1, #52
1	ldr	r4, [r2], #4
	str	r4, [r1], #4
	cmp	r1, r3
	bne	%B1

	mov	pc, lr


    [ :DEF:  CONFIG_S3C2410_NAND_BOOT
;
; copy_myself: copy vivi to ram
;
copy_myself
	mov	r10, lr

	; reset NAND
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =0xf830		; initial value
	str	r2, [r1, #oNFCONF]
	ldr	r2, [r1, #oNFCONF]
	bic	r2, r2, #0x800		; enable chip
	str	r2, [r1, #oNFCONF]
	mov	r2, #0xff		; RESET command
	strb	r2, [r1, #oNFCMD]
	mov	r3, #0			; wait 
1	add	r3, r3, #0x1
	cmp	r3, #0xa
	blt	%b1
2	ldr	r2, [r1, #oNFSTAT]	; wait ready
	tst	r2, #0x1
	beq	%b2
	ldr	r2, [r1, #oNFCONF]
	orr	r2, r2, #0x800		; disable chip
	str	r2, [r1, #oNFCONF]

	; get read to call C functions (for nand_read())
	ldr	sp, DW_STACK_START	; setup stack pointer
	mov	fp, #0			; no previous frame, so fp=0

	; copy vivi to RAM
	ldr	r0, =VIVI_RAM_BASE
	mov     r1, #0x0
	mov	r2, #0x20000
	bl	nand_read_ll

	tst	r0, #0x0
	beq	ok_nand_read
    [ :DEF: CONFIG_DEBUG_LL
bad_nand_read
	ldr	r0, STR_FAIL
	ldr	r1, SerBase
	bl	PrintWord
1	b	%b1		; infinite loop 
    ]
	
ok_nand_read
    [ :DEF:  CONFIG_DEBUG_LL
	ldr	r0, STR_OK
	ldr	r1, SerBase
	bl	PrintWord
    ]

	; verify
	mov	r0, #0
	ldr	r1, =0x33f00000
	mov	r2, #0x400	; 4 bytes * 1024 = 4K-bytes
go_next
	ldr	r3, [r0], #4
	ldr	r4, [r1], #4
	teq	r3, r4
	bne	notmatch
	subs	r2, r2, #4
	beq	done_nand_read	
	bne	go_next
notmatch
    [ :DEF:  CONFIG_DEBUG_LL
	sub	r0, r0, #4
	ldr	r1, SerBase
	bl	PrintHexWord
	ldr	r0, STR_FAIL
	ldr	r1, SerBase
	bl	PrintWord
    ]
1	b	%b1
done_nand_read

    [ :DEF:  CONFIG_DEBUG_LL
	ldr	r0, STR_OK
	ldr	r1, SerBase
	bl	PrintWord
    ]

	mov	pc, r10

; clear memory
; r0: start address
; r1: length
mem_clear
	mov	r2, #0
	mov	r3, r2
	mov	r4, r2
	mov	r5, r2
	mov	r6, r2
	mov	r7, r2
	mov	r8, r2
	mov	r9, r2

clear_loop
	stmia	r0!, {r2-r9}
	subs	r1, r1, #(8 * 4)
	bne	clear_loop

	mov	pc, lr

    ] ; CONFIG_S3C2410_NAND_BOOT


    [ :DEF:  CONFIG_BOOTUP_MEMTEST
;
; Simple memory test function
;
memtest
	mov	r10, lr

    [ :DEF:  CONFIG_DEBUG_LL
	mov	r0, #'M'
	ldr	r1, SerBase
	bl	PrintChar
	mov	r0, #'T'
	ldr	r1, SerBase
	bl	PrintChar
	mov	r0, #'S'
	ldr	r1, SerBase
	bl	PrintChar