📄 smdk2410.inc
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include config.inc include s3c2410.inc include sizes.inc; Porocessor memory map */ROM_BASE0 EQU 0x00000000 ;; base address of rom bank 0 */ROM_BASE1 EQU 0x08000000 ;; base address of rom bank 1 */DRAM_BASE0 EQU 0x30000000 ;; base address of dram bank 0 */DRAM_BASE1 EQU 0x38000000 ;; base address of dram bank 1 */ [ :DEF: CONFIG_MTD_CFI;; Flash */FLASH_BASE EQU ROM_BASE0FLASH_SIZE EQU SZ_32MFLASH_UNCACHED_BASE EQU 0x10000000 ;; to mapping flash memory */FLASH_BUSWIDTH EQU 4;; ROM */VIVI_ROM_BASE EQU 0x00000000VIVI_PRIV_ROM_BASE EQU 0x01FC0000 ] ;; CONFIG_MTD_CFI */ [ :DEF: CONFIG_S3C2410_NAND_BOOT;; Flash */FLASH_BASE EQU ROM_BASE0FLASH_SIZE EQU SZ_32MFLASH_UNCACHED_BASE EQU 0x10000000 ;; to mapping flash memory */FLASH_BUSWIDTH EQU 4;; ROM */VIVI_ROM_BASE EQU 0x00000000VIVI_PRIV_ROM_BASE EQU 0x01FC0000 ] ;; CONFIG_S3C2410_NAND_BOOT */ [ :DEF: CONFIG_S3C2410_AMD_BOOT;; Flash */FLASH_BASE EQU ROM_BASE0FLASH_SIZE EQU SZ_1MFLASH_UNCACHED_BASE EQU 0x10000000 ;; to mapping flash memory */FLASH_BUSWIDTH EQU 2 ;; 16-bit bus */;; ROM */VIVI_ROM_BASE EQU 0x00000000VIVI_PRIV_ROM_BASE EQU 0x01FC0000 ];; CONFIG_S3C2410_AMD_BOOT */DRAM_BASE EQU DRAM_BASE0DRAM_SIZE EQU SZ_64MMTD_PART_SIZE EQU SZ_16KMTD_PART_OFFSET EQU 0x00000000PARAMETER_TLB_SIZE EQU SZ_16KPARAMETER_TLB_OFFSET EQU 0x00004000LINUX_CMD_SIZE EQU SZ_16KLINUX_CMD_OFFSET EQU 0x00008000VIVI_PRIV_SIZE EQU MTD_PART_SIZE + PARAMETER_TLB_SIZE + LINUX_CMD_SIZE;; RAM */VIVI_RAM_SIZE EQU SZ_1MVIVI_RAM_BASE EQU DRAM_BASE + DRAM_SIZE - VIVI_RAM_SIZEHEAP_SIZE EQU SZ_1MHEAP_BASE EQU VIVI_RAM_BASE - HEAP_SIZEMMU_TABLE_SIZE EQU SZ_16KMMU_TABLE_BASE EQU HEAP_BASE - MMU_TABLE_SIZEVIVI_PRIV_RAM_BASE EQU MMU_TABLE_BASE - VIVI_PRIV_SIZESTACK_SIZE EQU SZ_32KSTACK_BASE EQU VIVI_PRIV_RAM_BASE - STACK_SIZERAM_SIZE EQU STACK_BASE - DRAM_BASERAM_BASE EQU DRAM_BASE;;* Architecture magic and machine type*/ include architecture.incMACH_TYPE EQU 193 ARCHITECTURE_MAGIC EQU ((ARM_PLATFORM << 24) | (ARM_S3C2410_CPU << 16) | \MACH_TYPE);;* 扁鸥 殿殿*/UART_BAUD_RATE EQU 115200FIN EQU 12000000;;* CPU 饭瘤胶磐 汲沥 蔼甸*/;; CPU clcok */;; 50.00 MHz */MDIV_50 EQU 0x5cPDIV_50 EQU 0x4SDIV_50 EQU 0x2;; 200.00 MHz */MDIV_200 EQU 0x5cPDIV_200 EQU 0x4SDIV_200 EQU 0x0;; initial values for DRAM */;; vBWSCON 0x22111120*/vBWSCON EQU 0x22111110vBANKCON0 EQU 0x00000700vBANKCON1 EQU 0x00000700vBANKCON2 EQU 0x00000700vBANKCON3 EQU 0x00000700vBANKCON4 EQU 0x00000700vBANKCON5 EQU 0x00000700vBANKCON6 EQU 0x00018005vBANKCON7 EQU 0x00018005vREFRESH EQU 0x008e0459vBANKSIZE EQU 0xb2vMRSRB6 EQU 0x30vMRSRB7 EQU 0x30vLOCKTIME EQU 0x00ffffff ;; It's a default value vCLKCON EQU 0x0000fff8 ;; It's a default value vCLKDIVN EQU 0x3 ;; FCLK:HCLK:PCLK = 1:2:4 */vMPLLCON_50 EQU ((MDIV_50 << 12) | (PDIV_50 << 4) | (SDIV_50)) vMPLLCON_200 EQU ((MDIV_200 << 12) | (PDIV_200 << 4) | (SDIV_200)) ;; initial values for serial */vULCON EQU 0x3 ;; UART, no parity, one stop bit, 8 bits */vUCON EQU 0x245vUFCON EQU 0x0vUMCON EQU 0x0;; inital values for GPIOs */vGPACON EQU 0x007fffffvGPBCON EQU 0x00044555vGPBUP EQU 0x000007ffvGPCCON EQU 0xaaaaaaaavGPCUP EQU 0x0000ffffvGPDCON EQU 0xaaaaaaaavGPDUP EQU 0x0000ffffvGPECON EQU 0xaaaaaaaavGPEUP EQU 0x0000ffffvGPFCON EQU 0x000055aavGPFUP EQU 0x000000ffvGPGCON EQU 0xff95ffbavGPGUP EQU 0x0000ffffUART_BRD EQU ((50000000 / (UART_BAUD_RATE * 16)) - 1)vGPHCON EQU 0x0016faaavGPHUP EQU 0x000007ffvEXTINT0 EQU 0x22222222vEXTINT1 EQU 0x22222222vEXTINT2 EQU 0x22222222;=======================================================INTOFFSET EQU 0x4a000014HandleEINT0 EQU 0x33ffff20 END⌨️ 快捷键说明
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