s3c2410.inc

ARM9 的head。BOOTLOAD和串口IO的部分 if.q if

USR26_MODE		EQU   0x00
FIQ26_MODE		EQU   0x01
IRQ26_MODE		EQU   0x02
SVC26_MODE		EQU   0x03
USR_MODE		EQU   0x10
FIQ_MODE		EQU   0x11
IRQ_MODE		EQU   0x12
SVC_MODE		EQU   0x13
ABT_MODE		EQU   0x17
UND_MODE		EQU   0x1b
SYSTEM_MODE		EQU   0x1f
MODE_MASK		EQU   0x1f
F_BIT			EQU   0x40
I_BIT			EQU   0x80
CC_V_BIT		EQU  (1 << 28)
CC_C_BIT		EQU  (1 << 29)
CC_Z_BIT		EQU  (1 << 30)
CC_N_BIT		EQU  (1 << 31)

;; Memory Controller ;;
MEM_CTL_BASE	EQU  0x48000000

;; Offset ;;
oBWSCON		EQU   0x00	;; R;W, Bus width and wait status ctrl reg. ;;
oBANKCON0		EQU   0x04	;; R;W, Bank 0 control reg. ;;
oBANKCON1		EQU   0x08	;; R;W, Bank 1 control reg. ;;
oBANKCON2		EQU   0x0C	;; R;W, Bank 2 control reg. ;;
oBANKCON3		EQU   0x10	;; R;W, Bank 3 control reg. ;;
oBANKCON4		EQU   0x14	;; R;W, Bank 4 control reg. ;;
oBANKCON5		EQU   0x18	;; R;W, Bank 5 control reg. ;;
oBANKCON6		EQU   0x1C	;; R;W, Bank 6 control reg. ;;
oBANKCON7		EQU   0x20	;; R;W, Bank 7 control reg. ;;
oREFRESH		EQU   0x24	;; R;W, SDRAM refresh control register ;;
oBANKSIZE		EQU   0x28	;; R;W, Flexible bank size register ;;
oMRSRB6		EQU   0x2C	;; R;W, Mode register set register bank 6 ;;
oMRSRB7		EQU   0x2C	;; R;W, Mode register set register bank 7 ;;


;; Bits ;;
SELF_REFRESH	EQU   (1 << 22)

;; Clock and Power Management ;;
CLK_CTL_BASE	EQU   0x4C000000

;; Offset ;;
oLOCKTIME		EQU   0x00	;; R;W, PLL lock time count register ;;
oMPLLCON		EQU   0x04	;; R;W, MPLL configuration register ;;
oUPLLCON		EQU   0x08	;; R;W, UPLL configuration register ;;
oCLKCON		EQU   0x0C	;; R;W, Clock generator control reg. ;;
oCLKSLOW		EQU   0x10	;; R;W, Slow clock control register ;;
oCLKDIVN		EQU   0x14	;; R;W, Clock divider control ;;


;; macros ;;
; GET_MDIV(x)		FExtr(x, fMPLL_MDIV)
; GET_PDIV(x)		FExtr(x, fMPLL_PDIV)
; GET_SDIV(x)		FExtr(x, fMPLL_SDIV)

;; GPIO ;;
GPIO_CTL_BASE		EQU   0x56000000

;; Offset ;;
oGPIO_CON			EQU   0x0	;; R;W, Configures the pins of the port ;;
oGPIO_DAT			EQU   0x4	;; R;W,	Data register for port ;;
oGPIO_UP			EQU   0x8	;; R;W, Pull-up disable register ;;
oGPIO_RESERVED		EQU   0xC	;; R;W, Reserved ;;
oGPIO_A			EQU   0x00
oGPIO_B			EQU   0x10
oGPIO_C			EQU   0x20
oGPIO_D			EQU   0x30
oGPIO_E			EQU   0x40
oGPIO_F			EQU   0x50
oGPIO_G			EQU   0x60
oGPIO_H			EQU   0x70
oMISCCR			EQU   0x80	;; R;W, Miscellaneous control register ;;
oDCLKCON			EQU   0x84	;; R;W, DCLK0;1 control register ;;
oEXTINT0			EQU   0x88	;; R;W, External interrupt control reg. 0 ;;
oEXTINT1			EQU   0x8C	;; R;W, External interrupt control reg. 1 ;;
oEXTINT2			EQU   0x90	;; R;W, External interrupt control reg. 2 ;;
oEINTFLT0			EQU   0x94	;; R;W, Reserved ;;
oEINTFLT1			EQU   0x98	;; R;W, Reserved ;;
oEINTFLT2			EQU   0x9C	;; R;W, External interrupt control reg. 2 ;;
oEINTFLT3			EQU   0xA0	;; R;W, External interrupt control reg. 3 ;;
oEINTMASK			EQU   0xA4	;; R;W, External interrupt mask register ;;
oEINTPEND			EQU   0xA8	;; R;W, External interrupt pending reg. ;;

;; UART ;;
UART_CTL_BASE		EQU   0x50000000
UART0_CTL_BASE		EQU   UART_CTL_BASE
UART1_CTL_BASE		EQU   UART_CTL_BASE + 0x4000
UART2_CTL_BASE		EQU   UART_CTL_BASE + 0x8000

;; Offset ;;
oULCON			EQU   0x00	;; R;W, UART line control register ;;
oUCON			EQU   0x04	;; R;W, UART control register ;;
oUFCON			EQU   0x08	;; R;W, UART FIFO control register ;;
oUMCON			EQU   0x0C	;; R;W, UART modem control register ;;
oUTRSTAT		EQU   0x10	;; R  , UART Tx;Rx status register ;;
oUERSTAT		EQU   0x14	;; R  , UART Rx error status register ;;
oUFSTAT		EQU   0x18	;; R  , UART FIFO status register ;;
oUMSTAT		EQU   0x1C	;; R  , UART Modem status register ;;
oUTXHL			EQU   0x20	;;   W, UART transmit(little-end) buffer ;;
oUTXHB			EQU   0x23	;;   W, UART transmit(big-end) buffer ;;
oURXHL			EQU   0x24	;; R  , UART receive(little-end) buffer ;;
oURXHB			EQU   0x27	;; R  , UART receive(big-end) buffer ;;
oUBRDIV		EQU   0x28	;; R;W, Baud rate divisor register ;;

;; ... ;;
UTRSTAT_TX_EMPTY	EQU   (1 << 2)
UTRSTAT_RX_READY	EQU   (1 << 0)
UART_ERR_MASK		EQU   0xF 

;; Interrupts ;;
INT_CTL_BASE		EQU   0x4A000000

;; Offset ;;
oSRCPND			EQU   0x00
oINTMOD			EQU   0x04
oINTMSK			EQU   0x08
oPRIORITY			EQU   0x0a
oINTPND			EQU   0x10
oINTOFFSET			EQU   0x14
oSUBSRCPND			EQU   0x18
oINTSUBMSK			EQU   0x1C
;; Registers ;;

INT_ADCTC		EQU   (1 << 31)	;; ADC EOC interrupt ;;
INT_RTC			EQU   (1 << 30)	;; RTC alarm interrupt ;;
INT_SPI1		EQU   (1 << 29)	;; UART1 transmit interrupt ;;
INT_UART0		EQU   (1 << 28)	;; UART0 transmit interrupt ;;
INT_IIC			EQU   (1 << 27)	;; IIC interrupt ;;
INT_USBH		EQU   (1 << 26)	;; USB host interrupt ;;
INT_USBD		EQU   (1 << 25)	;; USB device interrupt ;;
INT_RESERVED24		EQU   (1 << 24)
INT_UART1		EQU   (1 << 23)	;; UART1 receive interrupt ;;
INT_SPI0		EQU   (1 << 22)	;; SPI interrupt ;;
INT_MMC			EQU   (1 << 21)	;; MMC interrupt ;;
INT_DMA3		EQU   (1 << 20)	;; DMA channel 3 interrupt ;;
INT_DMA2		EQU   (1 << 19)	;; DMA channel 2 interrupt ;;
INT_DMA1		EQU   (1 << 18)	;; DMA channel 1 interrupt ;;
INT_DMA0		EQU   (1 << 17)	;; DMA channel 0 interrupt ;;
INT_LCD			EQU   (1 << 16)	;; reserved for future use ;;
INT_UART2		EQU   (1 << 15)	;; UART 2 interrupt  ;;
INT_TIMER4		EQU   (1 << 14)	;; Timer 4 interrupt ;;
INT_TIMER3		EQU   (1 << 13)	;; Timer 3 interrupt ;;
INT_TIMER2		EQU   (1 << 12)	;; Timer 2 interrupt ;;
INT_TIMER1		EQU   (1 << 11)	;; Timer 1 interrupt ;;
INT_TIMER0		EQU   (1 << 10)	;; Timer 0 interrupt ;;
INT_WDT			EQU   (1 << 9)	;; Watch-Dog timer interrupt ;;
INT_TICK		EQU   (1 << 8)	;; RTC time tick interrupt  ;;
INT_BAT_FLT		EQU   (1 << 7)
INT_RESERVED6		EQU   (1 << 6)	;; Reserved for future use ;;
INT_EINT8_23		EQU   (1 << 5)	;; External interrupt 8 ~ 23 ;;
INT_EINT4_7		EQU   (1 << 4)	;; External interrupt 4 ~ 7 ;;
INT_EINT3		EQU   (1 << 3)	;; External interrupt 3 ;;
INT_EINT2		EQU   (1 << 2)	;; External interrupt 2 ;;
INT_EINT1		EQU   (1 << 1)	;; External interrupt 1 ;;
INT_EINT0		EQU   (1 << 0)	;; External interrupt 0 ;;

INT_ADC			EQU   (1 << 10)
INT_TC			EQU   (1 << 9)
INT_ERR2		EQU   (1 << 8)
INT_TXD2		EQU   (1 << 7)
INT_RXD2		EQU   (1 << 6)
INT_ERR1		EQU   (1 << 5)
INT_TXD1		EQU   (1 << 4)
INT_RXD1		EQU   (1 << 3)
INT_ERR0		EQU   (1 << 2)
INT_TXD0		EQU   (1 << 1)
INT_RXD0		EQU   (1 << 0)

;; NAND Flash Controller ;;
NAND_CTL_BASE		EQU   0x4E000000

;; Offset ;;
oNFCONF			EQU   0x00
oNFCMD				EQU   0x04
oNFADDR			EQU   0x08
oNFDATA			EQU   0x0c
oNFSTAT			EQU   0x10
oNFECC				EQU   0x14


;; PWM Timer ;;





TCON_4_AUTO        EQU        (1 << 22)       ;; auto reload on;off for Timer 4 ;;
TCON_4_UPDATE      EQU        (1 << 21)       ;; manual Update TCNTB4 ;;
TCON_4_ONOFF       EQU        (1 << 20)       ;; 0: Stop, 1: start Timer 4 ;;
COUNT_4_ON         EQU        (TCON_4_ONOFF|1)
COUNT_4_OFF        EQU        (TCON_4_ONOFF|0)
TCON_3_AUTO     	EQU   		(1 << 19)       ;; auto reload on;off for Timer 3 ;;
TIMER3_ATLOAD_ON   EQU        (TCON_3_AUTO/1)

;TIMER3_ATLAOD_OFF  EQU        FClrBit(TCON, TCON_3_AUTO)
TCON_3_INVERT   EQU   (1 << 18)       ;; 1: Inverter on for TOUT3 ;;
TIMER3_IVT_ON   EQU   (TCON_3_INVERT|1)

TCON_3_MAN      EQU   (1 << 17)       ;; manual Update TCNTB3,TCMPB3 ;;
TIMER3_MANUP    EQU   (TCON_3_MAN|1)

TCON_3_ONOFF    EQU   (1 << 16)       ;; 0: Stop, 1: start Timer 3 ;;
TIMER3_ON       EQU   (TCON_3_ONOFF|1)


NFSTAT_RnB      EQU   (1 << 0)
NFSTAT_nFWE     EQU   (1 << 8)
NFSTAT_nFRE     EQU   (1 << 9)
NFSTAT_ALE      EQU   (1 << 10)
NFSTAT_CLE      EQU   (1 << 11)
NFSTAT_AUTOBOOT EQU   (1 << 15)


;;
; Power Management
;;
SPI_CLK		EQU   (1 << 18)
IIS_CLK		EQU   (1 << 17)
IIC_CLK		EQU   (1 << 16)
ADC_CLK		EQU   (1 << 15)
RTC_CLK		EQU   (1 << 14)
GPIO_CLK		EQU   (1 << 13)
UART2_CLK		EQU   (1 << 12)
UART1_CLK		EQU   (1 << 11)
UART0_CLK		EQU   (1 << 10)
SDI_CLK		EQU   (1 << 9)
PWM_CLK		EQU   (1 << 8)
USBSLAVE_CLK	EQU   (1 << 7)
USBHOST_CLK	EQU   (1 << 6)
LCDC_CLK		EQU   (1 << 5)
NANDCTL_CLK	EQU   (1 << 4)
SLEEP_ON		EQU   (1 << 3)
IDLE			EQU   (1 << 2)




SCLKE		EQU   (1 << 19)
SCLK1		EQU   (1 << 18)
SCLK0		EQU   (1 << 17)
USBSPD1	EQU   (1 << 13)
USBSPD0	EQU   (1 << 12)
PMST_HWR	EQU   (1 << 0)
PMST_SMR	EQU   (1 << 1)
PMST_WDR	EQU   (1 << 2)

;;
; Watch-dog tiemr
;;




BWSCON_DW_8	EQU   0x0		;; set bus width to  8bit ;;
BWSCON_DW_16	EQU   0x1		;; set bus width to 16bit ;;
BWSCON_DW_32	EQU   0x2		;; set bus width to 32bit ;;

	END