case20.asm

这是一个68k的编译器

*
immed	equ	5
anyea	equ	$1234
index   equ     100
*
bd      equ     $1234           base displacement
od      equ     $5678           outer displacement
abs     equ     $7ABC           absolute address
longabs equ     $13579BDF       long absolute address
*
	org	$10000
*
*       Effective address tests
*
	tst     d0
	tst     a0
	tst     (a0)
	tst     (a0)+
	tst     -(a0)
	tst     index(a0)
	tst     (index,a0)
	tst     abs.w
	tst     abs.l
	tst     #immed
	tst     index+*(PC)
	tst     (index+*,PC)
*
*       The tough ones: indexed indirect
*
	tst     ([bd,a0,d0],od)
	tst     ([bd,a0],d0,od)
	tst     ([bd])
	tst     ([bd],od)
	tst     ([a0,d0])
	tst     ([bd,a0,d0])
	tst     ([a0,d0],od)
	tst     ([d0])
	tst     ([bd,d0])
	tst     ([d0],od)
	tst     ([bd,d0],od)
	tst     ([bd],d0)
	tst     ([bd],d0,od)
	tst     ([a0],d0)
	tst     ([bd,a0],d0)
	tst     ([a0],d0,od)
*
*       supressed base register cases
*
	tst     ([bd,za0,d0],od)
	tst     ([bd,za0],d0,od)
	tst     ([za0,d0])
	tst     ([bd,za0,d0])
	tst     ([za0,d0],od)
	tst     ([za0],d0)
	tst     ([bd,za0],d0)
	tst     ([za0],d0,od)
*
*       supressed index register
*
	tst     ([bd,a0,zd0],od)
	tst     ([bd,a0],zd0,od)
	tst     ([a0,zd0])
	tst     ([bd,a0,zd0])
	tst     ([a0,zd0],od)
	tst     ([zd0])
	tst     ([bd,zd0])
	tst     ([zd0],od)
	tst     ([bd,zd0],od)
	tst     ([bd],zd0)
	tst     ([bd],zd0,od)
	tst     ([a0],zd0)
	tst     ([bd,a0],zd0)
	tst     ([a0],zd0,od)
*
*       pc relative
*
	tst     ([bd,pc,d0],od)
	tst     ([bd,pc],d0,od)
	tst     ([pc,d0])
	tst     ([bd,pc,d0])
	tst     ([pc,d0],od)
	tst     ([pc],d0)
	tst     ([bd,pc],d0)
	tst     ([pc],d0,od)
*
*       supressed pc relative
*
	tst     ([bd,zpc,d0],od)
	tst     ([bd,zpc],d0,od)
	tst     ([zpc,d0])
	tst     ([bd,zpc,d0])
	tst     ([zpc,d0],od)
	tst     ([zpc],d0)
	tst     ([bd,zpc],d0)
	tst     ([zpc],d0,od)
*
*       supressed base reg and index reg.
*
	tst     ([bd,za0,zd0],od)
	tst     ([bd,za0],zd0,od)
	tst     ([za0,zd0])
	tst     ([bd,za0,zd0])
	tst     ([za0,zd0],od)
	tst     ([za0],zd0)
	tst     ([bd,za0],zd0)
	tst     ([za0],zd0,od)
*
*       index register scaling
*
	tst     ([d0.w*1])
	tst     ([d0.w*2])
	tst     ([d0.w*4])
	tst     ([d0.w*8])
	tst     ([d0.l*1])
	tst     ([d0.l*2])
	tst     ([d0.l*4])
	tst     ([d0.l*8])
*
*       all values for index reg
*
	tst     ([d0.w*1])
	tst     ([d1.w*1])
	tst     ([d2.w*1])
	tst     ([d3.w*1])
	tst     ([d4.w*1])
	tst     ([d5.w*1])
	tst     ([d6.w*1])
	tst     ([d7.w*1])
	tst     ([zd0.w*1])
	tst     ([zd1.w*1])
	tst     ([zd2.w*1])
	tst     ([zd3.w*1])
	tst     ([zd4.w*1])
	tst     ([zd5.w*1])
	tst     ([zd6.w*1])
	tst     ([zd7.w*1])
*
*       forced size on base disp./outer disp.
*
	tst     ([bd.w],od.w)
	tst     ([bd.l],od.w)
	tst     ([bd.w],od.l)
	tst     ([bd.l],od.l)
*
*       a very long instruction
*
	move.l  ([bd.l,a0,d0.l*8],od.l),([bd.l,sp,d7.l*8],od.l)
*
*       68020 instruction set tests
*
	abcd.b          d0,d0
	abcd            d0,d0
	abcd.b          -(a0),-(a0)
	abcd            -(a0),-(a0)
	add.b           #immed,(a4)
	add.w           #immed,(a4)
	add.l           #immed,(a4)
	add             #immed,(a4)
	add.w           anyea,d0
	add.l           anyea,d0
	add             anyea,d0
	add.b           (a6),d0
	add.b           d0,(a2)
	add.w           d0,(a2)
	add.l           d0,(a2)
	add             d0,(a2)
	adda            anyea,a0
	adda.w          anyea,a0
	adda.l          anyea,a0
	addi.b          #immed,(a4)
	addi.w          #immed,(a4)
	addi.l          #immed,(a4)
	addi            #immed,(a4)
	addq.b          #immed,(a5)
	addq.w          #immed,(a5)
	addq.l          #immed,(a5)
	addq            #immed,(a5)
	addx.b          d0,d0
	addx.w          d0,d0
	addx.l          d0,d0
	addx            d0,d0
	addx.b          -(a0),-(a0)
	addx.w          -(a0),-(a0)
	addx.l          -(a0),-(a0)
	addx            -(a0),-(a0)
	and.b           (a6),d0
	and.w           (a6),d0
	and.l           (a6),d0
	and             (a6),d0
	and.b           d0,(a2)
	and.w           d0,(a2)
	and.l           d0,(a2)
	and             d0,(a2)
	and.b           #immed,(a4)
	and.w           #immed,(a4)
	and.l           #immed,(a4)
	and             #immed,(a4)
	and.b           #immed,CCR
	and             #immed,CCR
	and.w           #immed,SR
	and             #immed,SR
	andi.b          #immed,(a4)
	andi.w          #immed,(a4)
	andi.l          #immed,(a4)
	andi            #immed,(a4)
	andi.b          #immed,CCR
	andi            #immed,CCR
	andi.w          #immed,SR
	andi            #immed,SR
	asl.w           (a2)
	asl             (a2)
	asl.b           d0,d0
	asl.w           d0,d0
	asl.l           d0,d0
	asl             d0,d0
	asl.b           #immed,d0
	asl.w           #immed,d0
	asl.l           #immed,d0
	asl             #immed,d0
	asr.w           (a2)
	asr             (a2)
	asr.b           d0,d0
	asr.w           d0,d0
	asr.l           d0,d0
	asr             d0,d0
	asr.b           #immed,d0
	asr.w           #immed,d0
	asr.l           #immed,d0
	asr             #immed,d0
bcclabel
	bcc.b           bcclabel
	bcc.w           bcclabel
	bcc.l           bcclabel
	bcc             bcclabel
	bcs             bcclabel
	beq             bcclabel
	bge             bcclabel
	bgt             bcclabel
	bhi             bcclabel
	ble             bcclabel
	bls             bcclabel
	blt             bcclabel
	bmi             bcclabel
	bne             bcclabel
	bpl             bcclabel
	bvc             bcclabel
	bvs             bcclabel
	bra             bcclabel
	bsr             bcclabel
	bchg.l          d0,d0
	bchg            d0,d0
	bchg.l          #immed,d0
	bchg            #immed,d0
	bchg            d0,(a0)
	bchg            #immed,(a0)
	bclr            d0,d0
	bclr            #immed,d0
	bclr            d0,(a0)
	bclr            #immed,(a0)
	bset            d0,d0
	bset            #immed,d0
	bset            d0,(a0)
	bset            #immed,(a0)
	btst            d0,d0
	btst            #immed,d0
	btst            d0,(a6)
	btst            #immed,(a6)
*
	bfchg           (a1){d0:d0}
	bfchg           (a1){d0:immed}
	bfchg           (a1){immed:d0}
	bfchg           (a1){immed:immed}
	bfclr           (a1){d0:immed}
	bfexts          d0{d0:immed},d0
	bfexts          (a0){d0:immed},d0
	bfextu          d0{d0:immed},d0
	bfextu          (a0){d0:immed},d0
	bfffo           d0{d0:immed},d0
	bfffo           (a0){d0:immed},d0
	bfins           d0,(a1){d0:immed}
	bfset           (a1){d0:immed}
	bftst           d0{d0:immed}
	bftst           (a0){d0:immed}
	bkpt            #immed
	callm           #immed,(a0)
	cas.b           d0,d0,(a2)
	cas.w           d0,d0,(a2)
	cas.l           d0,d0,(a2)
	cas             d0,d0,(a2)
	cas2.w          d0:D1,d0:D1,(A5):(d0)
	cas2.l          d0:D1,d0:D1,(A5):(d0)
	cas2            d0:D1,d0:D1,(A5):(d0)
	cas2            d0:d1,d2:d3,(d4):(d5)
	chk.w           (a6),d0
	chk.l           (a6),d0
	chk             (a6),d0
	chk2.b          (a0),a0
	chk2.w          (a0),a0
	chk2.l          (a0),a0
	chk2            (a0),a0
	chk2.b          (a0),d0
	chk2.w          (a0),d0
	chk2.l          (a0),d0
	chk2            (a0),d0
	clr.b           (a4)
	clr.w           (a4)
	clr.l           (a4)
	clr             (a4)
	cmp.b           #immed,(a6)
	cmp.w           #immed,(a6)
	cmp.l           #immed,(a6)
	cmp             #immed,(a6)
	cmp.w           anyea,d0
	cmp.l           anyea,d0
	cmp             anyea,d0
	cmp.b           (a6),d0
	cmpa.w          anyea,a0
	cmpa.l          anyea,a0
	cmpa            anyea,a0
	cmpi.b          #immed,(a6)
	cmpi.w          #immed,(a6)
	cmpi.l          #immed,(a6)
	cmpi            #immed,(a6)
	cmpm.b          (a0)+,(a0)+
	cmpm.w          (a0)+,(a0)+
	cmpm.l          (a0)+,(a0)+
	cmpm            (a0)+,(a0)+
	cmp2.b          (a0),a0
	cmp2.w          (a0),a0
	cmp2.l          (a0),a0
	cmp2            (a0),a0
	cmp2.b          (a0),d0
	cmp2.w          (a0),d0
	cmp2.l          (a0),d0
	cmp2            (a0),d0
dbcclabel
	dbcc            d0,dbcclabel
	dbcs            d0,dbcclabel
	dbeq            d0,dbcclabel
	dbf             d0,dbcclabel
	dbge            d0,dbcclabel
	dbgt            d0,dbcclabel
	dbhi            d0,dbcclabel
	dble            d0,dbcclabel
	dbls            d0,dbcclabel
	dblt            d0,dbcclabel
	dbmi            d0,dbcclabel
	dbne            d0,dbcclabel
	dbpl            d0,dbcclabel
	dbt             d0,dbcclabel
	dbvc            d0,dbcclabel
	dbvs            d0,dbcclabel
	dbra            d0,dbcclabel
	divs.w          (a6),d0
	divs            (a6),d0
	divs.l          (a6),d0
	divs.l          (a6),d0:D1
	divsl.l         (a6),d0:D1
	divsl           (a6),d0:D1
	divu.w          (a6),d0
	divu            (a6),d0
	divu.l          (a6),d0
	divu.l          (a6),d0:D1
	divul.l         (a6),d0:D1
	divul           (a6),d0:D1
	eor.b           d0,(a4)
	eor.w           d0,(a4)
	eor.l           d0,(a4)
	eor             d0,(a4)
	eor.b           #immed,(a4)
	eor.w           #immed,(a4)
	eor.l           #immed,(a4)
	eor             #immed,(a4)
	eor.b           #immed,CCR
	eor             #immed,CCR
	eor.w           #immed,SR
	eor             #immed,SR
	eori.b          #immed,(a4)
	eori.w          #immed,(a4)
	eori.l          #immed,(a4)
	eori            #immed,(a4)
	eori.b          #immed,CCR
	eori            #immed,CCR
	eori.w          #immed,SR
	eori            #immed,SR
	exg.l           d0,d0
	exg             d0,d0
	exg.l           a0,a0
	exg             a0,a0
	exg.l           d0,a0
	exg             d0,a0
	exg.l           a0,d0
	exg             a0,d0
*
	exg             d0,d1
	exg             d0,a1
	exg             a0,d1
	exg             a0,a1
*
	ext.w           d0
	ext             d0
	ext.l           d0
	extb.l          d0
	extb            d0
	illegal
	jmp             (a0)
	jsr             (a0)
	lea.l           (a0),a0
	lea             (a0),a0
	link.w          a0,#immed
	link            a0,#immed
	link.l          a0,#immed
	lsl.w           (a2)
	lsl             (a2)
	lsl.b           d0,d0
	lsl.w           d0,d0
	lsl.l           d0,d0
	lsl             d0,d0
	lsl.b           #immed,d0
	lsl.w           #immed,d0
	lsl.l           #immed,d0
	lsl             #immed,d0
	lsr.w           (a2)
	lsr             (a2)
	lsr.b           d0,d0
	lsr.w           d0,d0
	lsr.l           d0,d0
	lsr             d0,d0
	lsr.b           #immed,d0
	lsr.w           #immed,d0
	lsr.l           #immed,d0
	lsr             #immed,d0
	move.w          anyea,(a4)
	move            anyea,(a4)
	move.b          (a6),(a4)
	move.l          anyea,(a4)
	move.w          anyea,a0
	move            anyea,a0
	move.l          anyea,a0
	move.w          CCR,(a4)
	move            CCR,(a4)
	move.w          (a6),CCR
	move            (a6),CCR
	move.w          SR,(a4)
	move            SR,(a4)
	move.w          (a6),SR
	move            (a6),SR
	move.l          usp,a0