vectors.asm

This code ports the uC/OS operating system by Jean LaBrosse to the TI TMS320C2xx family of DSP s.

	.page
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Module    :   vectors.asm
;
; Purpose   :   vectors to software and hardware ISR's.
;
; Language  :   TMS320C1x/C2x/C2xx/C5x COFF Assembler       Version 6.60
;				Copyright (c) 1987-1995  Texas Instruments Incorporated
;
; Written   :
;
; Modified  :   Kirby W. Cartwright, The Vanner Power Group, 07/23/98
;
; Project   :   Vanner Power Group Modular Controller Project PX-2.
;
; Copyright :	Copyright (c) 1988-1995 Texas Instruments Inc.
;				Copyright (c) 1998 by Vanner, Inc.  All Rights Reserved.
;
; Notes     :	"If additional interrupts have C interrupt handlers (in addition to the
;  				RESET vector), add the appropriate branches to the table below as indicated
;  				in the comment for each vector.  Vectors that have no interrupt routine
;  				should be handled with EINT and RET instructions."
;
; Unit Tested:	7/27/98, KWC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		.include f240regs.h
        .global _c_int0, _OSTickISR, RESET, _OSCtxSw

        .asect  "vectors",0

RESET   B	_c_int0						; power-on, external, and watch dog resets.
										; need to see which happened.

;
; Hardware, maskable, interrupt vectors.
;

INT1    B  _OSTickISR					; "high-priority" external interrupts
       									; 1, 2, and 3; and "real-time" interrupt.

INT2    EINT               				; B  _c_int2
        RET

INT3    EINT               				; B  _c_int3
        RET

INT4    EINT               				; B  _c_int4
        RET

INT5    EINT               				; B  _c_int5
        RET

INT6    EINT               				; B  _c_int6
        RET

        NOP								; skip the reserved interrupt.
        NOP

;
; Software interrupt vectors.
;

INT8    EINT               				; B  _c_int8
        RET

INT9    EINT               				; B  _c_int9
        RET

INT10   EINT               				; B  _c_int10
        RET

INT11   EINT               				; B  _c_int11
        RET

INT12   EINT               				; B  _c_int12
        RET

INT13   EINT               				; B  _c_int13
        RET

INT14   EINT               				; B  _c_int14
        RET

INT15   EINT               				; B  _c_int15
        RET

INT16   EINT               				; B  _c_int16
        RET

;
; Trap instruction vector.
;

TRAP	NOP
		RET								; B  _Trap

;
; Non-maskable interrupt vector.
;

NMI_VECT	EINT                   		; B	_Nmi
		RET

        NOP								; skip the reserved interrupt.
        NOP

;
; Still more software interrupt vectors.
;

INT20   EINT               				; B  _c_int20
        RET

INT21   EINT               				; B  _c_int21
        RET

INT22   EINT               				; B  _c_int22
        RET

INT23   EINT               				; B  _c_int23
        RET

INT24   EINT               				; B  _c_int24
        RET

INT25   EINT               				; B  _c_int25
        RET

INT26   EINT               				; B  _c_int26
        RET

INT27   EINT               				; B  _c_int27
        RET

INT28   EINT               				; B  _c_int28
        RET

INT29   EINT               				; B  _c_int29
        RET

INT30   EINT               				; B  _c_int30
        RET

INT31	B	_OSCtxSw					; task switching service vector.

        .end