📄 lock.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
port(
clk : in std_logic;
kin : in std_logic;
kout : out std_logic);
end lock;
architecture a of lock is
begin
process(clk)
variable i1 : std_logic;
variable i2 : std_logic;
begin
if(clk'event and clk='1') then
i1 := i2;
i2 := kin;
if (i1=i2) then
kout <= i2;
end if;
end if;
end process;
end;
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