📄 show.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity show is
port( clk : in std_logic;
time1: in std_logic_vector(5 downto 0);
time2 : in std_logic_vector(5 downto 0);
sel : out std_logic_vector(1 to 4);
show:out std_logic_vector(0 to 6));
end show;
architecture a of show is
signal i : std_logic_vector(3 downto 0);
signal sel1 : std_logic_vector(1 to 4);
begin
process(clk)
begin
if (clk'event and clk='1')then ---片选信号:时分复用
case sel1 is
when "0111"=>
sel1<="1110";
i<="00"&time1(5 downto 4);
when "1110"=>
sel1<="1101";
i<=time1(3 downto 0);
when "1101"=>
sel1<="1011";
i<="00"&time2(5 downto 4);
when "1011"=>
sel1<="0111";
i<=time2(3 downto 0);
when others=>
sel1<="0111";
end case;
end if;
end process;
sel<=sel1;
show <= "1110011" when i="1001" else
"1111111" when i="1000" else
"1110000" when i="0111" else
"0011111" when i="0110" else
"1011011" when i="0101" else
"0110011" when i="0100" else
"1111001" when i="0011" else
"1101101" when i="0010" else
"0110000" when i="0001" else
"1111110";
end;
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