📄 control.rpt
字号:
Project Information g:\traffic lights\control.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 12/04/2004 00:09:56
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CONTROL
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
control EPM7128SLC84-15 3 18 0 67 15 52 %
User Pins: 3 18 0
Project Information g:\traffic lights\control.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information g:\traffic lights\control.rpt
** FILE HIERARCHY **
|lpm_add_sub:249|
|lpm_add_sub:249|addcore:adder|
|lpm_add_sub:249|addcore:adder|addcore:adder0|
|lpm_add_sub:249|altshift:result_ext_latency_ffs|
|lpm_add_sub:249|altshift:carry_ext_latency_ffs|
|lpm_add_sub:249|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1071|
|lpm_add_sub:1071|addcore:adder|
|lpm_add_sub:1071|addcore:adder|addcore:adder0|
|lpm_add_sub:1071|altshift:result_ext_latency_ffs|
|lpm_add_sub:1071|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1071|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1102|
|lpm_add_sub:1102|addcore:adder|
|lpm_add_sub:1102|addcore:adder|addcore:adder0|
|lpm_add_sub:1102|altshift:result_ext_latency_ffs|
|lpm_add_sub:1102|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1102|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1372|
|lpm_add_sub:1372|addcore:adder|
|lpm_add_sub:1372|addcore:adder|addcore:adder0|
|lpm_add_sub:1372|altshift:result_ext_latency_ffs|
|lpm_add_sub:1372|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1372|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1403|
|lpm_add_sub:1403|addcore:adder|
|lpm_add_sub:1403|addcore:adder|addcore:adder0|
|lpm_add_sub:1403|altshift:result_ext_latency_ffs|
|lpm_add_sub:1403|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1403|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1625|
|lpm_add_sub:1625|addcore:adder|
|lpm_add_sub:1625|addcore:adder|addcore:adder0|
|lpm_add_sub:1625|altshift:result_ext_latency_ffs|
|lpm_add_sub:1625|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1625|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1656|
|lpm_add_sub:1656|addcore:adder|
|lpm_add_sub:1656|addcore:adder|addcore:adder0|
|lpm_add_sub:1656|altshift:result_ext_latency_ffs|
|lpm_add_sub:1656|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1656|altshift:oflow_ext_latency_ffs|
Device-Specific Information: g:\traffic lights\control.rpt
control
***** Logic for device 'control' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R
E E E E E E E E E E E E
S S S S S S V S S S S S S
E E E E E E C E E E V E E E
R R R R R R C R R R C R R R
c V V V G V V V I G G G c G V V V C V V V
l E E E N E E E N N N N l N E E E I E E E
r D D D D D D D T D D D k D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
kin | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | RESERVED
GND | 19 67 | RESERVED
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | RESERVED
RESERVED | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | time25
VCCIO | 26 60 | time24
RESERVED | 27 59 | GND
RESERVED | 28 58 | time21
RESERVED | 29 57 | time15
RESERVED | 30 56 | time14
RESERVED | 31 55 | time12
GND | 32 54 | time11
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V c c c G V t t t G t t c c c V
E E E E E C a a a N C i i i N i i a a a C
S S S S S C t t t D C m m m D m m t t t C
E E E E E I c c c I e e e e e c c c I
R R R R R O h h h N 1 1 2 2 2 h h h O
V V V V V _ _ _ T 0 3 0 2 3 _ _ _
E E E E E o o o o o o
D D D D D 4 5 6 1 3 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: g:\traffic lights\control.rpt
control
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 3/16( 18%) 3/ 8( 37%) 0/16( 0%) 3/36( 8%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 8/16( 50%) 19/36( 52%)
F: LC81 - LC96 16/16(100%) 8/ 8(100%) 12/16( 75%) 16/36( 44%)
G: LC97 - LC112 16/16(100%) 1/ 8( 12%) 6/16( 37%) 14/36( 38%)
H: LC113 - LC128 16/16(100%) 0/ 8( 0%) 6/16( 37%) 21/36( 58%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 24/64 ( 37%)
Total logic cells used: 67/128 ( 52%)
Total shareable expanders used: 15/128 ( 11%)
Total Turbo logic cells used: 67/128 ( 52%)
Total shareable expanders not available (n/a): 17/128 ( 13%)
Average fan-in: 5.88
Total fan-in: 394
Total input pins required: 3
Total fast input logic cells required: 0
Total output pins required: 18
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 67
Total flipflops required: 38
Total product terms required: 217
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 1/ 128 ( 0%)
Device-Specific Information: g:\traffic lights\control.rpt
control
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
11 (5) (A) INPUT 0 0 0 0 0 0 15 clr
12 (3) (A) INPUT 0 0 0 0 0 0 15 kin
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\traffic lights\control.rpt
control
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
50 75 E FF + t 0 0 0 0 1 0 0 catch_o1
52 80 E FF + t 0 0 0 0 1 0 0 catch_o2
51 77 E FF + t 0 0 0 0 1 0 0 catch_o3
39 53 D FF + t 0 0 0 0 1 0 0 catch_o4
40 51 D FF + t 0 0 0 0 1 0 0 catch_o5
41 49 D FF + t 0 0 0 0 1 0 0 catch_o6
44 65 E FF + t 0 0 0 0 3 0 0 time10
54 83 F FF + t 0 0 0 0 6 0 0 time11
55 85 F FF + t 2 1 1 0 6 0 0 time12
45 67 E FF + t 4 2 1 0 8 0 0 time13
56 86 F FF + t 3 1 1 0 9 0 0 time14
57 88 F FF + t 4 2 1 0 9 0 0 time15
46 69 E FF + t 0 0 0 0 3 0 0 time20
58 91 F FF + t 0 0 0 0 6 0 0 time21
48 72 E FF + t 2 1 1 0 6 0 0 time22
49 73 E FF + t 4 2 1 0 8 0 0 time23
60 93 F FF + t 3 1 1 0 9 0 0 time24
61 94 F FF + t 4 2 1 0 9 0 0 time25
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\traffic lights\control.rpt
control
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -