📄 traffic.rpt
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| | | | | | | | | | | | | +----- LC99 showout6
| | | | | | | | | | | | | | +--- LC103 |show:u6|i2
| | | | | | | | | | | | | | | +- LC98 |show:u6|i1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC103-> - - - - - - - * * * * * * * * - | - - - - - - * - | <-- |show:u6|i2
LC98 -> - - - - - - - * * * * * * * - * | - - - - - - * - | <-- |show:u6|i1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC34 -> - - - - - - - - - - - - - - - * | - - - - - - * - | <-- |control:u5|:16
LC91 -> - - - - - - - - - - - - - - * - | - - - - - - * - | <-- |control:u5|:22
LC89 -> - - - - - - - - - - - - - - - * | - - - - - - * - | <-- |control:u5|:24
LC33 -> - - - - - - - - - - - - - - - * | - - - - - - * - | <-- |control:u5|:28
LC81 -> - - - - - - - - - - - - - - * - | - - - - - - * - | <-- |control:u5|:34
LC84 -> - - - - - - - - - - - - - - - * | - - - - - - * - | <-- |control:u5|:36
LC55 -> - * - - - * - - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter5
LC56 -> - * - - - * - - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter4
LC57 -> * * * - * * - - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter3
LC74 -> * * * * * * - - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter2
LC75 -> * * - * * * - - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter1
LC76 -> * * - - - - * - - - - - - - - - | - - - * * - * - | <-- |control:u5|counter0
LC113-> - - - - - * * - - - - - - - - - | - * * * * * * - | <-- |feng1:u1|s
LC83 -> - - - - - - - - - - - - - - * * | - - - - - * * - | <-- selout1
LC85 -> - - - - - - - - - - - - - - * * | - - - - - * * - | <-- selout2
LC86 -> - - - - - - - - - - - - - - * * | - - - - - * * - | <-- selout3
LC88 -> - - - - - - - - - - - - - - * * | - - - - - * * - | <-- selout4
LC90 -> - - - - - - - * * * * * * * - - | - - - - - * * - | <-- |show:u6|i3
LC92 -> - - - - - - - * * * * * * * - - | - - - - - * * - | <-- |show:u6|i0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC119 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC124 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC116 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3
| | | +------------------------- LC126 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4
| | | | +----------------------- LC115 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
| | | | | +--------------------- LC127 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
| | | | | | +------------------- LC113 |feng1:u1|s
| | | | | | | +----------------- LC125 |feng1:u1|i6
| | | | | | | | +--------------- LC122 |feng1:u1|i5
| | | | | | | | | +------------- LC120 |feng1:u1|i4
| | | | | | | | | | +----------- LC128 |feng1:u1|i3
| | | | | | | | | | | +--------- LC114 |feng1:u1|i2
| | | | | | | | | | | | +------- LC117 |feng1:u1|i1
| | | | | | | | | | | | | +----- LC118 |feng1:u1|i0
| | | | | | | | | | | | | | +--- LC121 |lock:u3|:3
| | | | | | | | | | | | | | | +- LC123 |lock:u3|i2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC119-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1
LC124-> - - - - - - - - - - - * - - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2
LC116-> - - - - - - - - - - * - - - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3
LC126-> - - - - - - - - - * - - - - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4
LC115-> - - - - - - - - * - - - - - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
LC127-> - - - - - - - * - - - - - - - - | - - - - - - - * | <-- |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
LC125-> - - - - - * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i6
LC122-> - - - - * * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i5
LC120-> - - - * * * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i4
LC128-> - - * * * * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i3
LC114-> - * * * * * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i2
LC117-> * * * * * * * * * * * * * - - - | - - - - - - - * | <-- |feng1:u1|i1
LC118-> * * * * * * * * * * * * * * - - | - - - - - - - * | <-- |feng1:u1|i0
LC121-> - - - - - - - - - - - - - - * - | - - - * * - - * | <-- |lock:u3|:3
LC123-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |lock:u3|i2
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
12 -> - - - - - - - - - - - - - - * * | - - - - - - - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** EQUATIONS **
clk : INPUT;
reset : INPUT;
special : INPUT;
-- Node name is 'catch1' = '|control:u5|:4'
-- Equation name is 'catch1', type is output
catch1 = DFFE( _LC077 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'catch2' = '|control:u5|:6'
-- Equation name is 'catch2', type is output
catch2 = DFFE( _LC066 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'catch3' = '|control:u5|:8'
-- Equation name is 'catch3', type is output
catch3 = DFFE( _LC068 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'catch4' = '|control:u5|:10'
-- Equation name is 'catch4', type is output
catch4 = DFFE( _LC071 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'catch5' = '|control:u5|:12'
-- Equation name is 'catch5', type is output
catch5 = DFFE( _LC073 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'catch6' = '|control:u5|:14'
-- Equation name is 'catch6', type is output
catch6 = DFFE( _LC078 $ GND, _LC113, VCC, VCC, VCC);
-- Node name is 'selout1' = '|show:u6|sel11'
-- Equation name is 'selout1', type is output
selout1 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = selout1 & selout2 & !selout3 & selout4
# selout1 & selout2 & selout3 & !selout4
# !selout1 & selout2 & selout3 & selout4;
-- Node name is 'selout2' = '|show:u6|sel12'
-- Equation name is 'selout2', type is output
selout2 = DFFE( _EQ002 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = selout1 & selout2 & !selout3 & selout4;
-- Node name is 'selout3' = '|show:u6|sel13'
-- Equation name is 'selout3', type is output
selout3 = DFFE( _EQ003 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = selout1 & selout2 & selout3 & !selout4;
-- Node name is 'selout4' = '|show:u6|sel14'
-- Equation name is 'selout4', type is output
selout4 = DFFE( _EQ004 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !selout1 & selout2 & selout3 & selout4;
-- Node name is 'showout0'
-- Equation name is 'showout0', location is LC105, type is output.
showout0 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC090 & _LC092 & !_LC098 & !_LC103
# !_LC090 & !_LC092 & _LC103;
-- Node name is 'showout1'
-- Equation name is 'showout1', location is LC101, type is output.
showout1 = LCELL( _EQ006 $ VCC);
_EQ006 = !_LC090 & !_LC092 & _LC098 & _LC103
# !_LC090 & _LC092 & !_LC098 & _LC103;
-- Node name is 'showout2'
-- Equation name is 'showout2', location is LC097, type is output.
showout2 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC090 & !_LC092 & _LC098 & !_LC103;
-- Node name is 'showout3'
-- Equation name is 'showout3', location is LC109, type is output.
showout3 = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC090 & _LC092 & _LC098 & _LC103
# !_LC090 & !_LC092 & !_LC098 & _LC103
# _LC092 & !_LC098 & !_LC103;
-- Node name is 'showout4'
-- Equation name is 'showout4', location is LC107, type is output.
showout4 = LCELL( _EQ009 $ VCC);
_EQ009 = _LC092 & !_LC098 & !_LC103
# !_LC090 & !_LC098 & _LC103
# !_LC090 & _LC092;
-- Node name is 'showout5'
-- Equation name is 'showout5', location is LC104, type is output.
showout5 = LCELL( _EQ010 $ VCC);
_EQ010 = !_LC090 & _LC092 & _LC098 & _LC103
# !_LC090 & !_LC092 & _LC098 & !_LC103
# !_LC090 & _LC092 & !_LC103;
-- Node name is 'showout6'
-- Equation name is 'showout6', location is LC099, type is output.
showout6 = LCELL( _EQ011 $ !_LC090);
_EQ011 = !_LC090 & _LC092 & _LC098 & _LC103
# !_LC098 & !_LC103;
-- Node name is '|control:u5|:40' = '|control:u5|catch1'
-- Equation name is '_LC077', type is buried
_LC077 = DFFE( _EQ012 $ GND, _LC113, !_LC061, VCC, VCC);
_EQ012 = _LC053 & !_LC055 & !_LC056 & !_LC057 & _LC070 & !_LC074 &
!_LC075 & !_LC076 & !_LC121
# _LC077 & !_LC121 & _X001
# _LC077 & _LC121;
_X001 = EXP(!_LC055 & !_LC056 & !_LC057 & !_LC074 & !_LC075 & !_LC076);
-- Node name is '|control:u5|:41' = '|control:u5|catch2'
-- Equation name is '_LC066', type is buried
_LC066 = DFFE( _EQ013 $ GND, _LC113, !_LC061, VCC, VCC);
_EQ013 = !_LC053 & !_LC055 & !_LC056 & !_LC057 & !_LC070 & !_LC074 &
!_LC075 & !_LC076 & !_LC079 & !_LC121
# _LC066 & !_LC121 & _X001
# _LC066 & _LC121;
_X001 = EXP(!_LC055 & !_LC056 & !_LC057 & !_LC074 & !_LC075 & !_LC076);
-- Node name is '|control:u5|:42' = '|control:u5|catch3'
-- Equation name is '_LC068', type is buried
_LC068 = DFFE( _EQ014 $ VCC, _LC113, VCC, !_LC061, VCC);
_EQ014 = !_LC053 & !_LC055 & !_LC056 & !_LC057 & !_LC070 & !_LC074 &
!_LC075 & !_LC076 & !_LC079 & !_LC121
# _LC053 & !_LC055 & !_LC056 & !_LC057 & _LC070 & !_LC074 &
!_LC075 & !_LC076 & !_LC121
# !_LC068 & _X002;
_X002 = EXP(!_LC055 & !_LC056 & !_LC057 & !_LC074 & !_LC075 & !_LC076 &
!_LC121);
-- Node name is '|control:u5|:43' = '|control:u5|catch4'
-- Equation name is '_LC071', type is buried
_LC071 = DFFE( _EQ015 $ GND, _LC113, !_LC061, VCC, VCC);
_EQ015 = !_LC053 & !_LC055 & !_LC056 & !_LC057 & _LC070 & !_LC074 &
!_LC075 & !_LC076 & !_LC121
# _LC071 & !_LC121 & _X001
# _LC071 & _LC121;
_X001 = EXP(!_LC055 & !_LC056 & !_LC057 & !_LC074 & !_LC075 & !_LC076);
-- Node name is '|control:u5|:44' = '|control:u5|catch5'
-- Equation name is '_LC073', type is buried
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