📄 traffic.rpt
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Total logic cells required: 96
Total flipflops required: 58
Total product terms required: 354
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 62
Synthesized logic cells: 2/ 128 ( 1%)
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
12 (3) (A) INPUT 0 0 0 0 0 0 2 reset
11 (5) (A) INPUT 0 0 0 0 0 0 2 special
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
41 49 D FF t 0 0 0 0 2 0 0 catch1
52 80 E FF t 0 0 0 0 2 0 0 catch2
44 65 E FF t 0 0 0 0 2 0 0 catch3
48 72 E FF t 0 0 0 0 2 0 0 catch4
46 69 E FF t 0 0 0 0 2 0 0 catch5
45 67 E FF t 0 0 0 0 2 0 0 catch6
54 83 F FF + t 0 0 0 0 4 4 5 selout1 (|show:u6|:25)
55 85 F FF + t 0 0 0 0 4 4 5 selout2 (|show:u6|:26)
56 86 F FF + t 0 0 0 0 4 4 5 selout3 (|show:u6|:27)
57 88 F FF + t 0 0 0 0 4 4 5 selout4 (|show:u6|:28)
68 105 G OUTPUT t 0 0 0 0 4 0 0 showout0
65 101 G OUTPUT t 0 0 0 0 4 0 0 showout1
63 97 G OUTPUT t 0 0 0 0 4 0 0 showout2
70 109 G OUTPUT t 0 0 0 0 4 0 0 showout3
69 107 G OUTPUT t 0 0 0 0 4 0 0 showout4
67 104 G OUTPUT t 0 0 0 0 4 0 0 showout5
64 99 G OUTPUT t 0 0 0 0 4 0 0 showout6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 111 G SOFT t 0 0 0 0 4 0 1 |control:u5|LPM_ADD_SUB:249|addcore:adder|addcore:adder0|result_node3
- 106 G SOFT t 0 0 0 0 6 0 1 |control:u5|LPM_ADD_SUB:249|addcore:adder|addcore:adder0|result_node5
(71) 112 G SOFT t 0 0 0 0 2 0 2 |control:u5|LPM_ADD_SUB:1071|addcore:adder|addcore:adder0|g4
(33) 64 D SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1071|addcore:adder|addcore:adder0|result_node5
- 108 G SOFT t 0 0 0 0 2 0 1 |control:u5|LPM_ADD_SUB:1102|addcore:adder|addcore:adder0|gcp2
- 110 G SOFT t 0 0 0 0 3 0 2 |control:u5|LPM_ADD_SUB:1102|addcore:adder|addcore:adder0|g4
- 54 D SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1102|addcore:adder|addcore:adder0|result_node5
- 50 D SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|gcp2
- 95 F SOFT t 0 0 0 0 4 0 2 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|g4
- 42 C SOFT t 0 0 0 0 2 0 1 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|result_node4
(27) 43 C SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|result_node5
(40) 51 D SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|gcp2
(62) 96 F SOFT t 0 0 0 0 4 0 2 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|g4
- 41 C SOFT t 0 0 0 0 2 0 1 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|result_node4
(25) 45 C SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|result_node5
(35) 59 D SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|gcp2
(61) 94 F SOFT t 0 0 0 0 4 0 2 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|g4
- 47 C SOFT t 0 0 0 0 2 0 1 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|result_node4
(28) 40 C SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|result_node5
(29) 38 C SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|gcp2
(30) 37 C SOFT t 0 0 0 0 4 0 2 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|g4
- 36 C SOFT t 0 0 0 0 2 0 1 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|result_node4
(31) 35 C SOFT t 0 0 0 0 3 0 1 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|result_node5
- 34 C DFFE t 6 1 1 0 10 0 1 |control:u5|:16
- 30 B DFFE t 6 1 1 0 10 0 1 |control:u5|:18
- 44 C DFFE t 5 0 0 0 9 0 1 |control:u5|:20
(58) 91 F DFFE t 3 1 1 0 7 0 1 |control:u5|:22
- 89 F DFFE t 1 0 1 0 7 0 1 |control:u5|:24
- 82 F DFFE t 0 0 0 0 4 0 1 |control:u5|:26
- 33 C DFFE t 6 1 1 0 10 0 1 |control:u5|:28
(22) 17 B DFFE t 6 1 1 0 10 0 1 |control:u5|:30
- 18 B DFFE t 5 0 0 0 9 0 1 |control:u5|:32
- 81 F DFFE t 3 1 1 0 7 0 1 |control:u5|:34
- 84 F DFFE t 1 0 1 0 7 0 1 |control:u5|:36
- 87 F DFFE t 0 0 0 0 4 0 1 |control:u5|:38
(51) 77 E DFFE t 2 1 1 0 12 1 1 |control:u5|catch1 (|control:u5|:40)
- 66 E DFFE t 2 1 1 0 13 1 1 |control:u5|catch2 (|control:u5|:41)
- 68 E DFFE t 2 1 1 0 13 1 1 |control:u5|catch3 (|control:u5|:42)
- 71 E DFFE t 2 1 1 0 12 1 1 |control:u5|catch4 (|control:u5|:43)
(49) 73 E DFFE t 2 1 1 0 12 1 1 |control:u5|catch5 (|control:u5|:44)
- 78 E DFFE t 2 1 1 0 12 1 1 |control:u5|catch6 (|control:u5|:45)
(39) 53 D TFFE t 0 0 0 0 10 0 20 |control:u5|i1 (|control:u5|:46)
- 70 E TFFE t 1 0 1 0 12 0 24 |control:u5|i0 (|control:u5|:47)
- 55 D DFFE t 1 0 1 0 10 0 22 |control:u5|counter5 (|control:u5|:48)
(37) 56 D TFFE t 2 0 1 0 10 0 22 |control:u5|counter4 (|control:u5|:49)
(36) 57 D DFFE t 1 0 1 0 10 0 23 |control:u5|counter3 (|control:u5|:50)
- 74 E TFFE t 3 1 1 0 12 0 24 |control:u5|counter2 (|control:u5|:51)
(50) 75 E DFFE t 2 0 1 0 10 0 23 |control:u5|counter1 (|control:u5|:52)
- 76 E DFFE t 1 0 1 0 10 0 17 |control:u5|counter0 (|control:u5|:53)
- 63 D DFFE t 3 1 1 0 8 0 6 |control:u5|t15 (|control:u5|:55)
- 62 D DFFE t 3 1 1 0 8 0 10 |control:u5|t14 (|control:u5|:56)
- 60 D DFFE t 6 1 1 0 7 0 14 |control:u5|t13 (|control:u5|:57)
- 100 G DFFE t 2 0 1 0 6 0 18 |control:u5|t12 (|control:u5|:58)
- 52 D DFFE t 1 0 1 0 6 0 18 |control:u5|t11 (|control:u5|:59)
- 102 G DFFE t 0 0 0 0 2 0 20 |control:u5|t10 (|control:u5|:60)
- 79 E LCELL s t 0 0 0 0 3 0 5 |control:u5|~850~1
- 119 H SOFT t 0 0 0 0 2 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1
- 124 H SOFT t 0 0 0 0 3 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2
- 116 H SOFT t 0 0 0 0 4 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3
(80) 126 H SOFT t 0 0 0 0 5 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4
(73) 115 H SOFT t 0 0 0 0 6 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
- 127 H SOFT t 0 0 0 0 7 0 1 |feng1:u1|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
- 113 H TFFE + t 0 0 0 0 7 6 32 |feng1:u1|s (|feng1:u1|:3)
(79) 125 H DFFE + t 0 0 0 0 8 0 8 |feng1:u1|i6 (|feng1:u1|:4)
- 122 H DFFE + t 0 0 0 0 8 0 9 |feng1:u1|i5 (|feng1:u1|:5)
(76) 120 H DFFE + t 0 0 0 0 8 0 10 |feng1:u1|i4 (|feng1:u1|:6)
(81) 128 H DFFE + t 0 0 0 0 8 0 11 |feng1:u1|i3 (|feng1:u1|:7)
- 114 H DFFE + t 0 0 0 0 8 0 12 |feng1:u1|i2 (|feng1:u1|:8)
(74) 117 H DFFE + t 0 0 0 0 8 0 13 |feng1:u1|i1 (|feng1:u1|:9)
(75) 118 H TFFE + t 0 0 0 0 0 0 13 |feng1:u1|i0 (|feng1:u1|:10)
- 121 H DFFE + t 0 0 0 1 2 0 16 |lock:u3|:3
(77) 123 H DFFE + t 0 0 0 1 0 0 1 |lock:u3|i2 (|lock:u3|:6)
(34) 61 D DFFE + t 0 0 0 1 2 0 16 |lock:u4|:3
- 58 D DFFE + t 0 0 0 1 0 0 1 |lock:u4|i2 (|lock:u4|:6)
- 90 F DFFE + t 5 0 1 0 7 7 1 |show:u6|i3 (|show:u6|:29)
- 103 G DFFE + t 5 0 1 0 7 7 1 |show:u6|i2 (|show:u6|:30)
- 98 G DFFE + t 8 0 1 0 9 7 1 |show:u6|i1 (|show:u6|:31)
- 92 F DFFE + t 3 0 1 0 9 7 2 |show:u6|i0 (|show:u6|:32)
(60) 93 F SOFT s t 1 0 1 0 6 0 1 |show:u6|~452~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC30 |control:u5|:18
| +--- LC17 |control:u5|:30
| | +- LC18 |control:u5|:32
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
83 -> - - - | - - - - - - - - | <-- clk
LC42 -> * - - | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|result_node4
LC41 -> * - - | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|result_node4
LC59 -> - - * | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|gcp2
LC47 -> - * - | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|result_node4
LC38 -> - - * | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|gcp2
LC36 -> - * - | - * - - - - - - | <-- |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|result_node4
LC53 -> * * * | - * * - * * - - | <-- |control:u5|i1
LC70 -> * * * | - * * * * * - - | <-- |control:u5|i0
LC62 -> * * - | - * * - - - - - | <-- |control:u5|t14
LC60 -> * * * | - * * - - * - - | <-- |control:u5|t13
LC100-> * * * | - * * * - * - - | <-- |control:u5|t12
LC52 -> * * * | - * * * - * - - | <-- |control:u5|t11
LC102-> * * * | - * * * - * - - | <-- |control:u5|t10
LC113-> * * * | - * * * * * * - | <-- |feng1:u1|s
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\traffic lights\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------- LC42 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|result_node4
| +----------------------- LC43 |control:u5|LPM_ADD_SUB:1372|addcore:adder|addcore:adder0|result_node5
| | +--------------------- LC41 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|result_node4
| | | +------------------- LC45 |control:u5|LPM_ADD_SUB:1403|addcore:adder|addcore:adder0|result_node5
| | | | +----------------- LC47 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|result_node4
| | | | | +--------------- LC40 |control:u5|LPM_ADD_SUB:1625|addcore:adder|addcore:adder0|result_node5
| | | | | | +------------- LC38 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|gcp2
| | | | | | | +----------- LC37 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|g4
| | | | | | | | +--------- LC36 |control:u5|LPM_ADD_SUB:1656|addcore:adder|addcore:adder0|result_node4
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