feng2.vhd

来自「1、 南北和东西方向各有一组绿、黄、红灯」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity feng2 is
port(
		clk:in std_logic;
		c_out:out std_logic);
end feng2;

architecture a of feng2 is
	signal s:std_logic;
begin
	process(clk)       
		variable i :std_logic_vector(6 downto 0);
	begin
 		if (clk'event and clk='1')then 
    	     if (i="1111101")then
                  i:="0000000";
                  s<=not s;
	         else i:=i+1;
  	         end if;
	    end if;
	end process;
	c_out<=s;
end;