📄 control.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port( clk:in std_logic;
clr:in std_logic;
kin:in std_logic;
catch_o:out std_logic_vector(1 to 6);
time1 : out std_logic_vector(5 downto 0);
time2 : out std_logic_vector(5 downto 0));
end control;
architecture a of control is
signal counter : std_logic_vector(5 downto 0);
signal t1 : std_logic_vector(5 downto 0);
signal i : integer range 0 to 3;
signal temp: std_logic;
signal catch: std_logic_vector(1 to 6);
begin
process(clr,clk)
begin
if (clr='1') then ----复位有
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