traffic.vhd

来自「1、 南北和东西方向各有一组绿、黄、红灯」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity traffic is
port(
		clk:in std_logic;
        reset: in std_logic;
        special: in std_logic;
		catch:out std_logic_vector(1 to 6);
        selout: out std_logic_vector(1 to 4);
        showout:out std_logic_vector(0 to 6));
end traffic;
architecture a of traffic is
component feng1
port(	clk:in std_logic;
		c_out:out std_logic);
end component;
component feng2
port(	clk:in std_logic;
		c_out:out std_logic);
end component;
component lock
	port(		clk  : in std_logic;
				kin	 : in std_logic;
				kout : out std_logic);
end component;
component control
port(		clk:in std_logic;
			clr:in std_logic;
			kin:in std_logic;
			catch_o:out std_logic_vector(1 to 6);
			time1 : out std_logic_vector(5 downto 0);
            time2 : out std_logic_vector(5 downto 0));
end component;
component show
port(   		clk	: in std_logic;
				time1:  in std_logic_vector(5 downto 0);
                time2 : in std_logic_vector(5 downto 0);
				sel : out std_logic_vector(1 to 4);
				show:out std_logic_vector(0 to 6));
end component;
signal cp1,cp2:std_logic;
signal clr,kin:std_logic;
signal time1,time2:std_logic_vector(5 downto 0);
begin
u1:feng1 port map(clk=>clk,c_out=>cp1);
u2:feng2 port map(clk=>cp1,c_out=>cp2);
u4:lock port map(clk=>clk,kin=>special,kout=>clr);
u3:lock port map(clk=>clk,kin=>reset,kout=>kin);
u5:control port map(cp1,clr,kin,catch,time1,time2);
u6:show port map(clk=>clk,time1=>time1,time2=>time2,sel=>selout,show=>showout);
end;