feng1.rpt

1、 南北和东西方向各有一组绿、黄、红灯

   -    114    H       SOFT      t        0      0   0    0    6    0    1  |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
   -    113    H       SOFT      t        0      0   0    0    7    0    1  |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
 (80)   126    H       DFFE   +  t        0      0   0    0    8    1    7  i6 (:4)
 (77)   123    H       DFFE   +  t        0      0   0    0    8    1    8  i5 (:5)
   -    122    H       DFFE   +  t        0      0   0    0    8    1    9  i4 (:6)
   -    121    H       DFFE   +  t        0      0   0    0    8    1   10  i3 (:7)
 (76)   120    H       DFFE   +  t        0      0   0    0    8    1   11  i2 (:8)
   -    119    H       DFFE   +  t        0      0   0    0    8    1   12  i1 (:9)
 (75)   118    H       TFFE   +  t        0      0   0    0    0    1   12  i0 (:10)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       g:\traffic lights\feng1.rpt
feng1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                     Logic cells placed in LAB 'H'
        +--------------------------- LC117 c_out
        | +------------------------- LC116 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1
        | | +----------------------- LC124 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2
        | | | +--------------------- LC125 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3
        | | | | +------------------- LC115 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4
        | | | | | +----------------- LC114 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
        | | | | | | +--------------- LC113 |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
        | | | | | | | +------------- LC126 i6
        | | | | | | | | +----------- LC123 i5
        | | | | | | | | | +--------- LC122 i4
        | | | | | | | | | | +------- LC121 i3
        | | | | | | | | | | | +----- LC120 i2
        | | | | | | | | | | | | +--- LC119 i1
        | | | | | | | | | | | | | +- LC118 i0
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC116-> - - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1
LC124-> - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2
LC125-> - - - - - - - - - - * - - - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3
LC115-> - - - - - - - - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4
LC114-> - - - - - - - - * - - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5
LC113-> - - - - - - - * - - - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6
LC126-> * - - - - - * * * * * * * - | - - - - - - - * | <-- i6
LC123-> * - - - - * * * * * * * * - | - - - - - - - * | <-- i5
LC122-> * - - - * * * * * * * * * - | - - - - - - - * | <-- i4
LC121-> * - - * * * * * * * * * * - | - - - - - - - * | <-- i3
LC120-> * - * * * * * * * * * * * - | - - - - - - - * | <-- i2
LC119-> * * * * * * * * * * * * * - | - - - - - - - * | <-- i1
LC118-> * * * * * * * * * * * * * * | - - - - - - - * | <-- i0

Pin
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       g:\traffic lights\feng1.rpt
feng1

** EQUATIONS **

clk      : INPUT;

-- Node name is 'c_out' = 's' 
-- Equation name is 'c_out', location is LC117, type is output.
 c_out   = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6;

-- Node name is ':10' = 'i0' 
-- Equation name is 'i0', location is LC118, type is buried.
i0       = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':9' = 'i1' 
-- Equation name is 'i1', location is LC119, type is buried.
i1       = DFFE( _EQ002 $  _LC116, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC116;

-- Node name is ':8' = 'i2' 
-- Equation name is 'i2', location is LC120, type is buried.
i2       = DFFE( _EQ003 $  _LC124, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC124;

-- Node name is ':7' = 'i3' 
-- Equation name is 'i3', location is LC121, type is buried.
i3       = DFFE( _EQ004 $  _LC125, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC125;

-- Node name is ':6' = 'i4' 
-- Equation name is 'i4', location is LC122, type is buried.
i4       = DFFE( _EQ005 $  _LC115, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC115;

-- Node name is ':5' = 'i5' 
-- Equation name is 'i5', location is LC123, type is buried.
i5       = DFFE( _EQ006 $  _LC114, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC114;

-- Node name is ':4' = 'i6' 
-- Equation name is 'i6', location is LC126, type is buried.
i6       = DFFE( _EQ007 $  _LC113, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  i0 & !i1 &  i2 &  i3 &  i4 &  i5 &  i6 &  _LC113;

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC116', type is buried 
_LC116   = LCELL( i1 $  i0);

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC124', type is buried 
_LC124   = LCELL( i2 $  _EQ008);
  _EQ008 =  i0 &  i1;

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC125', type is buried 
_LC125   = LCELL( i3 $  _EQ009);
  _EQ009 =  i0 &  i1 &  i2;

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC115', type is buried 
_LC115   = LCELL( i4 $  _EQ010);
  _EQ010 =  i0 &  i1 &  i2 &  i3;

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC114', type is buried 
_LC114   = LCELL( i5 $  _EQ011);
  _EQ011 =  i0 &  i1 &  i2 &  i3 &  i4;

-- Node name is '|LPM_ADD_SUB:40|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC113', type is buried 
_LC113   = LCELL( i6 $  _EQ012);
  _EQ012 =  i0 &  i1 &  i2 &  i3 &  i4 &  i5;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                g:\traffic lights\feng1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,048K