show.rpt

1、 南北和东西方向各有一组绿、黄、红灯

        | | | | | | | | | | +--------- LC122 i1
        | | | | | | | | | | | +------- LC113 i0
        | | | | | | | | | | | | +----- LC114 ~440~1
        | | | | | | | | | | | | | +--- LC121 ~446~1
        | | | | | | | | | | | | | | +- LC116 ~452~1
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC118-> * - - - - - - - * * * * * * * | - - - - - - * * | <-- sel1
LC119-> - * * * * * * * * - - - - - - | - - - - - - - * | <-- i3
LC127-> - * * * * * * * - - - - * - - | - - - - - - - * | <-- i2
LC122-> - * * * * * * * - - * - - * - | - - - - - - - * | <-- i1
LC113-> - * * * * * * * - - - * - - * | - - - - - - - * | <-- i0
LC114-> - - - - - - - - - * - - - - - | - - - - - - - * | <-- ~440~1
LC121-> - - - - - - - - - - * - - - - | - - - - - - - * | <-- ~446~1
LC116-> - - - - - - - - - - - * - - - | - - - - - - - * | <-- ~452~1

Pin
83   -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
17   -> - - - - - - - - - - - * - - - | - - - - - - - * | <-- time10
18   -> - - - - - - - - - - * - - - - | - - - - - - - * | <-- time11
20   -> - - - - - - - - - * - - - - - | - - - - - - - * | <-- time12
21   -> - - - - - - - - * - - - - - - | - - - - - - - * | <-- time13
4    -> - - - - - - - - - - - - - - * | - - - - - - - * | <-- time14
5    -> - - - - - - - - - - - - - * - | - - - - - - - * | <-- time15
6    -> - - - - - - - - - - - * - - - | - - - - - - - * | <-- time20
8    -> - - - - - - - - - - * - - - - | - - - - - - - * | <-- time21
12   -> - - - - - - - - - * - - - - - | - - - - - - - * | <-- time22
9    -> - - - - - - - - * - - - - - - | - - - - - - - * | <-- time23
10   -> - - - - - - - - - - - * - - - | - - - - - - - * | <-- time24
11   -> - - - - - - - - - - * - - - - | - - - - - - - * | <-- time25
LC105-> * - - - - - - - * * * * * * * | - - - - - - * * | <-- sel2
LC104-> * - - - - - - - * * * * * * * | - - - - - - * * | <-- sel3
LC101-> * - - - - - - - * * * * * * * | - - - - - - * * | <-- sel4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        g:\traffic lights\show.rpt
show

** EQUATIONS **

clk      : INPUT;
time10   : INPUT;
time11   : INPUT;
time12   : INPUT;
time13   : INPUT;
time14   : INPUT;
time15   : INPUT;
time20   : INPUT;
time21   : INPUT;
time22   : INPUT;
time23   : INPUT;
time24   : INPUT;
time25   : INPUT;

-- Node name is ':32' = 'i0' 
-- Equation name is 'i0', location is LC113, type is buried.
i0       = DFFE( _EQ001 $  _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !i0 & !_LC116 &  sel1 &  sel2 &  sel3 &  sel4 &  _X001 &  _X002
         # !_LC116 &  sel1 & !sel2 &  sel3 &  sel4 & !time20 &  _X001 & 
              _X002
         # !_LC116 &  sel1 &  sel2 & !sel3 &  sel4 & !time24 &  _X001 & 
              _X002
         # !_LC116 &  sel1 &  sel2 &  sel3 & !sel4 & !time10 &  _X001 & 
              _X002;
  _X001  = EXP(!i0 & !sel1 & !sel3);
  _X002  = EXP(!i0 & !sel1 & !sel2);
  _EQ002 = !_LC116 &  _X001 &  _X002;
  _X001  = EXP(!i0 & !sel1 & !sel3);
  _X002  = EXP(!i0 & !sel1 & !sel2);

-- Node name is ':31' = 'i1' 
-- Equation name is 'i1', location is LC122, type is buried.
i1       = DFFE( _EQ003 $  _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !i1 & !_LC121 &  sel1 &  sel2 &  sel3 &  sel4 &  _X003 &  _X004
         # !_LC121 &  sel1 & !sel2 &  sel3 &  sel4 & !time21 &  _X003 & 
              _X004
         # !_LC121 &  sel1 &  sel2 & !sel3 &  sel4 & !time25 &  _X003 & 
              _X004
         # !_LC121 &  sel1 &  sel2 &  sel3 & !sel4 & !time11 &  _X003 & 
              _X004;
  _X003  = EXP(!i1 & !sel1 & !sel3);
  _X004  = EXP(!i1 & !sel1 & !sel2);
  _EQ004 = !_LC121 &  _X003 &  _X004;
  _X003  = EXP(!i1 & !sel1 & !sel3);
  _X004  = EXP(!i1 & !sel1 & !sel2);

-- Node name is ':30' = 'i2' 
-- Equation name is 'i2', location is LC127, type is buried.
i2       = DFFE( _EQ005 $ !_LC114, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC114 &  sel1 & !sel2 &  sel3 &  sel4 & !time22
         # !_LC114 &  sel1 &  sel2 &  sel3 & !sel4 & !time12
         # !_LC114 &  sel1 &  sel2 & !sel3 &  sel4
         # !_LC114 & !sel1 &  sel2 &  sel3 &  sel4;

-- Node name is ':29' = 'i3' 
-- Equation name is 'i3', location is LC119, type is buried.
i3       = DFFE( _EQ006 $  _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  sel1 & !sel2 &  sel3 &  sel4 & !time23 &  _X005 &  _X006 &  _X007 & 
              _X008
         #  sel1 &  sel2 &  sel3 & !sel4 & !time13 &  _X005 &  _X006 &  _X007 & 
              _X008
         #  sel1 &  sel2 & !sel3 &  sel4 &  _X005 &  _X006 &  _X007 &  _X008
         # !sel1 &  sel2 &  sel3 &  sel4 &  _X005 &  _X006 &  _X007 &  _X008;
  _X005  = EXP(!i3 & !sel2 & !sel4);
  _X006  = EXP(!i3 &  sel2 &  sel4);
  _X007  = EXP(!i3 & !sel3);
  _X008  = EXP(!i3 & !sel1);
  _EQ007 =  _X005 &  _X006 &  _X007 &  _X008;
  _X005  = EXP(!i3 & !sel2 & !sel4);
  _X006  = EXP(!i3 &  sel2 &  sel4);
  _X007  = EXP(!i3 & !sel3);
  _X008  = EXP(!i3 & !sel1);

-- Node name is 'sel1' = 'sel11' 
-- Equation name is 'sel1', location is LC118, type is output.
 sel1    = DFFE( _EQ008 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  sel1 &  sel2 & !sel3 &  sel4
         #  sel1 &  sel2 &  sel3 & !sel4
         # !sel1 &  sel2 &  sel3 &  sel4;

-- Node name is 'sel2' = 'sel12' 
-- Equation name is 'sel2', location is LC105, type is output.
 sel2    = DFFE( _EQ009 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  sel1 &  sel2 & !sel3 &  sel4;

-- Node name is 'sel3' = 'sel13' 
-- Equation name is 'sel3', location is LC104, type is output.
 sel3    = DFFE( _EQ010 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  sel1 &  sel2 &  sel3 & !sel4;

-- Node name is 'sel4' = 'sel14' 
-- Equation name is 'sel4', location is LC101, type is output.
 sel4    = DFFE( _EQ011 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !sel1 &  sel2 &  sel3 &  sel4;

-- Node name is 'show0' 
-- Equation name is 'show0', location is LC117, type is output.
 show0   = LCELL( _EQ012 $  VCC);
  _EQ012 =  i0 & !i1 & !i2 & !i3
         # !i0 &  i2 & !i3;

-- Node name is 'show1' 
-- Equation name is 'show1', location is LC123, type is output.
 show1   = LCELL( _EQ013 $  VCC);
  _EQ013 = !i0 &  i1 &  i2 & !i3
         #  i0 & !i1 &  i2 & !i3;

-- Node name is 'show2' 
-- Equation name is 'show2', location is LC125, type is output.
 show2   = LCELL( _EQ014 $  VCC);
  _EQ014 = !i0 &  i1 & !i2 & !i3;

-- Node name is 'show3' 
-- Equation name is 'show3', location is LC128, type is output.
 show3   = LCELL( _EQ015 $  VCC);
  _EQ015 =  i0 &  i1 &  i2 & !i3
         # !i0 & !i1 &  i2 & !i3
         #  i0 & !i1 & !i2;

-- Node name is 'show4' 
-- Equation name is 'show4', location is LC126, type is output.
 show4   = LCELL( _EQ016 $  VCC);
  _EQ016 =  i0 & !i1 & !i2
         # !i1 &  i2 & !i3
         #  i0 & !i3;

-- Node name is 'show5' 
-- Equation name is 'show5', location is LC120, type is output.
 show5   = LCELL( _EQ017 $  VCC);
  _EQ017 =  i0 &  i1 &  i2 & !i3
         # !i0 &  i1 & !i2 & !i3
         #  i0 & !i2 & !i3;

-- Node name is 'show6' 
-- Equation name is 'show6', location is LC115, type is output.
 show6   = LCELL( _EQ018 $ !i3);
  _EQ018 =  i0 &  i1 &  i2 & !i3
         # !i1 & !i2;

-- Node name is '~440~1' 
-- Equation name is '~440~1', location is LC114, type is buried.
-- synthesized logic cell 
_LC114   = LCELL( _EQ019 $  GND);
  _EQ019 = !i2 &  sel2 &  sel4
         # !i2 & !sel2 & !sel4
         # !i2 & !sel3
         # !i2 & !sel1;

-- Node name is '~446~1' 
-- Equation name is '~446~1', location is LC121, type is buried.
-- synthesized logic cell 
_LC121   = LCELL( _EQ020 $  GND);
  _EQ020 = !sel1 &  sel2 &  sel3 &  sel4 & !time15
         # !i1 & !sel3 & !sel4
         # !i1 & !sel2 & !sel4
         # !i1 & !sel2 & !sel3
         # !i1 & !sel1 & !sel4;

-- Node name is '~452~1' 
-- Equation name is '~452~1', location is LC116, type is buried.
-- synthesized logic cell 
_LC116   = LCELL( _EQ021 $  GND);
  _EQ021 = !sel1 &  sel2 &  sel3 &  sel4 & !time14
         # !i0 & !sel3 & !sel4
         # !i0 & !sel2 & !sel4
         # !i0 & !sel2 & !sel3
         # !i0 & !sel1 & !sel4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                 g:\traffic lights\show.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,536K