gt64120.s

AMD的AU1200引导程序

	
/************************************************************************
 *
 *  gt64120.S
 *
 *  Galileo specific functions
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/
	
#include <sysdefs.h>
#include <mips.h>
#include <init.h>
#include <spd.h>
#include <pci_api.h>
#include <gt64120.h>

/************************************************************************
 *  Definitions
 ************************************************************************/
	
/* Parameters for setup_cpu_decode/setup_cpu_decode */
#define LO	a0
#define HI	a1
#define REGLO	a2
#define REGHI	a3

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/
	
	.set noreorder


/************************************************************************	
 *
 *                          gt64120_init
 *  Description :
 *  -------------
 *
 *  Initialise GT64120 just enough so that we can access PCI.
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = Base address to be used for access to Galileo registers.
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = error code (0 = OK)
 *  v1 = 1 -> Request software reset
 *
 ************************************************************************/
LEAF(gt64120_init)

	/* Default return values */
	move	v0, zero
	move	v1, zero
	
        /*  Verify that the GT64120 "Internal Space Decode" 
	 *  register may be accessed at the default address. 
	 *  This is the case after a hardware or software reset, 
	 *  but is NOT the case if the user issues "go bfc00000" 
	 *  command. This is because the mapping of the system controller
	 *  is changed below.
	 *  If we detect that the memory mapping of the system 
	 *  controller has been changed, we request a software reset.
	 */
	li	t0, KSEG1(GT_DEF_BASE)  /* Base address after a reset	*/

	GT_LW(  t1, GT_ISD_OFS, t0 )
	li	t2, GT_ISD_DEFAULT
	beq	t1, t2, 1f
	nop

	/* Request software reset */
	li	v1, 1
	jr	ra
	nop
1:		
	/* Setup where we want the Galileo registers to be addressed */
	srl	t1, a0, 21
	GT_SW(	t1, GT_ISD_OFS, t0 )
	move	t0, a0
	KSEG1A(t0)
	
	/* Setup GT64120 CPU interface */
	GT_LW(  t1, GT_CPU_OFS, t0 )
	li	t2, ~GT_CPU_WR_MSK
	and	t1, t2
	li	t2, GT_CPU_WR_DDDD << GT_CPU_WR_SHF
	or	t1, t2
	GT_SW(  t1, GT_CPU_OFS, t0 )

        /*  HW bug workaround: Extend BootCS mapping area to access FPGA without
	 *		       4 x access on CBUS per 1 x access from SysAD.
	 */
	li	t1, 0
	GT_SW(	t1, GT_CS3HD_OFS, t0 )
	li	t1, 0xf0
        GT_SW(  t1, GT_BOOTLD_OFS, t0 )
	li	t1, 0xff
        GT_SW(  t1, GT_BOOTHD_OFS, t0 )

	/* Setup byte/word swap */

#ifdef EB	
	li t1, 0x00401
#else
	li t1, 0x10001
#endif
	GT_SW( t1, GT_PCI0_CMD_OFS, t0 )

        /* Change retrycount to a value, which is not 0 */
	li      t1, 0x00ffffff
	GT_SW(  t1, GT_PCI0_TOR_OFS, t0 )

        /* Setup GT64120 to have Master capability */
	li	t1,  GT_CFGADDR_CFGEN_BIT			    |\
		    (PCI_BUS_LOCAL   << GT_CFGADDR_BUSNUM_SHF)      |\
		    (GT_DEV          << GT_CFGADDR_DEVNUM_SHF)      |\
		    (0               << GT_CFGADDR_FUNCNUM_SHF)     |\
		    ((PCI_SC >>2)    << GT_CFGADDR_REGNUM_SHF)
	GT_SW(  t1, GT_PCI0_CFGADDR_OFS, t0 )
	GT_LW(  t2, GT_PCI0_CFGDATA_OFS, t0 )

	li	t1, (PCI_SC_CMD_MS_BIT | \
                     PCI_SC_CMD_BM_BIT | \
                     PCI_SC_CMD_SERR_BIT )

        or      t2, t1

	li	t1,  GT_CFGADDR_CFGEN_BIT			    |\
		    (PCI_BUS_LOCAL   << GT_CFGADDR_BUSNUM_SHF)      |\
		    (GT_DEV          << GT_CFGADDR_DEVNUM_SHF)      |\
		    (0               << GT_CFGADDR_FUNCNUM_SHF)     |\
		    ((PCI_SC >> 2)   << GT_CFGADDR_REGNUM_SHF)
	
	GT_SW(	t1, GT_PCI0_CFGADDR_OFS, t0 )
	GT_SW(	t2, GT_PCI0_CFGDATA_OFS, t0 )

        /* Setup GT64120 PCI latency timer */
	li	t1,  GT_CFGADDR_CFGEN_BIT			    |\
		    (PCI_BUS_LOCAL   << GT_CFGADDR_BUSNUM_SHF)      |\
		    (GT_DEV          << GT_CFGADDR_DEVNUM_SHF)      |\
		    (0               << GT_CFGADDR_FUNCNUM_SHF)     |\
		    ((PCI_BHLC >> 2) << GT_CFGADDR_REGNUM_SHF)
	GT_SW(	t1, GT_PCI0_CFGADDR_OFS, t0 )
	GT_LW(	t2, GT_PCI0_CFGDATA_OFS, t0 )

	li	t1, (8 << PCI_BHLC_LT_SHF)
        or      t2, t1

	li	t1,  GT_CFGADDR_CFGEN_BIT			    |\
		    (PCI_BUS_LOCAL   << GT_CFGADDR_BUSNUM_SHF)      |\
		    (GT_DEV          << GT_CFGADDR_DEVNUM_SHF)      |\
		    (0               << GT_CFGADDR_FUNCNUM_SHF)     |\
		    ((PCI_BHLC >> 2) << GT_CFGADDR_REGNUM_SHF)
	
	GT_SW(	t1, GT_PCI0_CFGADDR_OFS, t0 )
	GT_SW(	t2, GT_PCI0_CFGDATA_OFS, t0 )

	jr	ra
	nop
	
END(gt64120_init)


/************************************************************************	
 *
 *                          gt64120_get_pcimem_base
 *  Description :
 *  -------------
 *
 *  Return base address for PCI memory cycles.
 *
 *  Parameters :
 *  ------------
 * 
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = Base address for PCI memory cycles
 *
 ************************************************************************/
LEAF(gt64120_get_pcimem_base)

        li      v0, GT_DEF_PCI0_MEM0_BASE
	jr	ra
	nop

END(gt64120_get_pcimem_base)


/************************************************************************	
 *
 *                          gt64120_get_max_sdram_bank
 *  Description :
 *  -------------
 *
 *  Return max SDRAM module bank size
 *
 *  Parameters :
 *  ------------
 * 
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = Max SDRAM module bank size
 *
 ************************************************************************/
LEAF(gt64120_get_max_sdram_bank)

        li	v0, GT_MAX_BANKSIZE
	jr	ra
	nop

END(gt64120_get_max_sdram_bank)


/************************************************************************	
 *
 *                          gt64120_config_write
 *  Description :
 *  -------------
 *
 *  Perform 32 bit PCI configuration write cycle on local bus.
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = device number (function 0 assumed)
 *  a1 = register
 *  a2 = data
 *  a3 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = 0 if OK
 *  v0 = ERROR_NB_CONFIG if not OK
 *
 ************************************************************************/
LEAF(gt64120_config_write)

        /* Clear cause register bits */
        GT_SW(  zero, GT_INTRCAUSE_OFS, a3 )

	/* Write to requested register */
	sll	t0, a0, GT_CFGADDR_DEVNUM_SHF
	srl	t1, a1, 2
	sll	t1, GT_CFGADDR_REGNUM_SHF
	or	t0, t1
	li	t1, GT_CFGADDR_CFGEN_BIT			     |\
		    (PCI_BUS_LOCAL        << GT_CFGADDR_BUSNUM_SHF)  |\
		    (0                    << GT_CFGADDR_FUNCNUM_SHF)
	or	t0, t1

	GT_SW(	t0, GT_PCI0_CFGADDR_OFS, a3 )
	GT_SW(	a2, GT_PCI0_CFGDATA_OFS, a3 )

        /* Check for master abort */
        GT_LW(  t0, GT_INTRCAUSE_OFS, a3 )
	li	t1, GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT
	and	t0, t1
	beq	t0, zero, 1f
	move	v0, zero
	li	v0, ERROR_NB_CONFIG
1:
	jr	ra
	nop
	
END(gt64120_config_write)


/************************************************************************	
 *
 *                          gt64120_config_read
 *  Description :
 *  -------------
 *
 *  Perform 32 bit PCI configuration read cycle on local bus.
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = device number (function 0 assumed)
 *  a1 = register
 *  a2 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = 0 if OK
 *  v0 = ERROR_NB_CONFIG if not OK
 *  v1 = data read (if OK)
 *
 ************************************************************************/
LEAF(gt64120_config_read)

        /* Clear cause register bits */
        GT_SW(  zero, GT_INTRCAUSE_OFS, a2 ) 

	/* Read from requested register */
	sll	t0, a0, GT_CFGADDR_DEVNUM_SHF
	srl	t1, a1, 2
	sll	t1, GT_CFGADDR_REGNUM_SHF
	or	t0, t1
	li	t1, GT_CFGADDR_CFGEN_BIT			     |\
		    (PCI_BUS_LOCAL        << GT_CFGADDR_BUSNUM_SHF)  |\
		    (0			  << GT_CFGADDR_FUNCNUM_SHF)
	or	t0, t1

	GT_SW(  t0, GT_PCI0_CFGADDR_OFS, a2 )
	GT_LW(	v1, GT_PCI0_CFGDATA_OFS, a2 )

        /* Check for master abort */
        GT_LW(  t0, GT_INTRCAUSE_OFS, a2 ) 
	li	t1, GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT
	and	t0, t1
	beq	t0, zero, 1f
	move	v0, zero
	li	v0, ERROR_NB_CONFIG
1:
	jr	ra
	nop

END(gt64120_config_read)
	

/************************************************************************	
 *
 *                          gt64120_configure_sdram
 *  Description :
 *  -------------
 *
 *  Setup GT64120 SDRAM configuration
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = Worst case (lowest) bus freq. (MHz) for setting timing parms.
 *  a1 = SDRAM device size (in Mbit)
 *  a2 = SDRAM device bank count (not the module bank count)
 *  a3 = Module bank 0 size
 *  t0 = Module bank 1 size
 *  t1 = base address of controller
 *
 *  Banks are mapped to GT64120 ranges the following way :	
 *
 *  bank0 -> SCSO
 *  bank1 -> SCS2
 *
 *  Return values :
 *  ---------------
 *
 *  0 :				No error.
 *  ERROR_NB_DECODE :		Illegal ranges requested.
 *  ERROR_SDRAM_CASLAT :	Module does not support CAS latency = 2.
 *  ERROR_SDRAM_BURSTLEN :	Module does not support burslength = 8.
 *  ERROR_SDRAM_ERRORCHECK :	Module requires ECC error check.
 *  ERROR_SDRAM_DEV_BANKS :	SDRAM devices have bank counts other 
 *				than than 2/4.
 *
 ************************************************************************/
LEAF(gt64120_configure_sdram)

#define RA	        s0
#define FREQ		s1
#define DEV_SIZE	s2
#define DEV_BANKS	s3
#define GTBASE		s4
#define ACCUM		s5
#define PARITY_SUPPORT	s6
#define BSIZE0		s7
#define BSIZE1		s8	

	move    RA,        ra
	move	FREQ,      a0
	move	DEV_SIZE,  a1
	move	DEV_BANKS, a2
	move	BSIZE0,	   a3
	move	BSIZE1,	   t0
	move	GTBASE,    t1

	/*  SDRAM Burst Mode register.
	 *  Leave all bits except "Burst Order" unchanged.
	 */
	GT_LW(  t0, GT_SDRAM_BM_OFS, GTBASE )
	li      t1, ~GT_SDRAM_BM_ORDER_MSK
	and	t0, t1
	li	t1, (GT_SDRAM_BM_ORDER_SUB << GT_SDRAM_BM_ORDER_SHF)
	or	t0, t1
	GT_SW(	t0, GT_SDRAM_BM_OFS, GTBASE )
	
	/* SDRAM Address Decode register */
	li	t0, GT_SDRAM_ADDRDECODE_ADDR_2
	GT_SW(	t0, GT_SDRAM_ADDRDECODE_OFS, GTBASE )

	/*  SDRAM Bank0 + Bank2 Parameters registers.
	 *  SRAS precharge and SRAS to SCAS delay are
	 *  set conservatively. They may later be optimised based
	 *  on RAM parameters and system frequency.
	 */

	li     ACCUM, (GT_SDRAM_B0_BW_64       << GT_SDRAM_B0_BW_SHF)	     |\
		      (GT_SDRAM_B0_SRASPRCHG_3 << GT_SDRAM_B0_SRASPRCHG_SHF) |\
		      (GT_SDRAM_B0_SRAS2SCAS_3 << GT_SDRAM_B0_SRAS2SCAS_SHF)
	
	/*  CAS latency field : Galileo only supports CAS latency = 2 */
	li	a0, SPD_CASLAT	/* CAS latency field in SPD device    */
	jal	sys_spd_read	/* v1 = CAS latencies supported byte  */
	nop
	bne	v0, zero, error_sdram
	nop
	and	t0, v1, SPD_CASLAT_2_BIT
	beq	t0, zero, error_sdram
	li	v0, ERROR_SDRAM_CASLAT

	ori	ACCUM, (GT_SDRAM_B0_CASLAT_2 << GT_SDRAM_B0_CASLAT_SHF)

sdram_size:

	/* Setup SDRAM device size (16MBit or 64/128Mbit) */
	li	t0, 16 * 1024 * 1024	/* 16 Mbit */
	beq	DEV_SIZE, t0, Mbit16
	nop
	ori	ACCUM, (GT_SDRAM_B0_SIZE_64M << GT_SDRAM_B0_SIZE_SHF)
	b	burstlen
	nop
Mbit16:	
	ori	ACCUM, (GT_SDRAM_B0_SIZE_16M << GT_SDRAM_B0_SIZE_SHF)

burstlen:	
		
	/* Burst length field : Galileo only supports burstlen = 8 */
	li	a0, SPD_BURSTLEN