syscon_core.c

AMD的AU1200引导程序

/************************************************************************
 *
 *  syscon_core.c
 *
 *  Core card specific parts of SYSCON module.
 *
 *  TBD : Writing these parameters are not supported for SEAD board.
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <syscon_api.h>
#include <syscon.h>
#include <syserror.h>
#include <product.h>
#include <sead.h>
#include <gt64120.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/* Pointer to array of objects */
static t_syscon_obj       *syscon_objects;

/************************************************************************
 *  Static function prototypes
 ************************************************************************/


/************************************************************************
 *  Implementation : Static functions registered for handling particular 
 *  SYSCON objects for particular core cards.
 ************************************************************************/


/************************************************************************
 *    board_systemram_refresh_cycles_gt64120_read
 ************************************************************************/
static UINT32
board_systemram_refresh_cycles_gt64120_read(
    void *param,
    void *data )
{
    UINT32 regval;

    GT_L32( sys_nb_base, GT_SDRAM_CFG_OFS, regval);

    *(UINT32 *)param = REGFIELD( regval, GT_SDRAM_CFG_REFINT );

    return OK;
}


/************************************************************************
 *    board_systemram_refresh_cycles_gt64120_write 
 ************************************************************************/
static UINT32
board_systemram_refresh_cycles_gt64120_write(
    void *param,
    void *data )
{
    UINT32 regval, refcount;
    
    refcount = MIN( GT_SDRAM_CFG_REFINT_MSK >> GT_SDRAM_CFG_REFINT_SHF,
		    *(UINT32 *)param );
    
    /* Read */
    GT_L32( sys_nb_base, GT_SDRAM_CFG_OFS, regval);

    /* Modify */
    regval &= ~GT_SDRAM_CFG_REFINT_MSK;
    regval |= (refcount << GT_SDRAM_CFG_REFINT_SHF);

    /* Write */
    GT_W32( sys_nb_base, GT_SDRAM_CFG_OFS, regval);

    return OK;
}


/************************************************************************
 *    board_systemram_refresh_cycles_sead_read
 ************************************************************************/
static UINT32
board_systemram_refresh_cycles_sead_read(
    void *param,
    void *data )
{
    UINT32 regval;

    regval = REG32(KSEG1(SEAD_SD_TREFRESH));

    *(UINT32 *)param = REGFIELD(regval, SEAD_SD_TREFRESH_TREF);

    return OK;
}

/************************************************************************
 *    board_systemram_srasprchg_cycles_gt64120_read
 ************************************************************************/
static UINT32
board_systemram_srasprchg_cycles_gt64120_read(
    void *param,
    void *data )
{
    UINT32 regval;

    GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval );

    switch( REGFIELD( regval, GT_SDRAM_B0_SRASPRCHG ) )
    {
      case GT_SDRAM_B0_SRASPRCHG_2 :
        *(UINT32 *)param = 2;
	break;
      case GT_SDRAM_B0_SRASPRCHG_3 :
        *(UINT32 *)param = 3;
	break;
      default : /* Should not happen */
        return ERROR_SYSCON_UNKNOWN_PARAM;
    }

    return OK;
}


/************************************************************************
 *    board_systemram_srasprchg_cycles_gt64120_write  
 ************************************************************************/
static UINT32
board_systemram_srasprchg_cycles_gt64120_write(
    void *param,
    void *data )
{
    UINT32 regval;
  
    /* Read */
    GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval);

    /* Modify */
    regval &= ~GT_SDRAM_B0_SRASPRCHG_MSK;

    regval |= ( ( ( *(UINT32 *)param <= 2 ) ? 
	           GT_SDRAM_B0_SRASPRCHG_2 : 
		   GT_SDRAM_B0_SRASPRCHG_3 ) << 
		      GT_SDRAM_B0_SRASPRCHG_SHF );

    /* Write */
    GT_W32( sys_nb_base, GT_SDRAM_B0_OFS, regval);

    return OK;
}


/************************************************************************
 *    board_systemram_srasprchg_cycles_sead_read
 ************************************************************************/
static UINT32
board_systemram_srasprchg_cycles_sead_read(
    void *param,
    void *data )
{
    UINT32 regval;

    regval = REG32(KSEG1(SEAD_SD_LATENCIES));

    *(UINT32 *)param = REGFIELD(regval, SEAD_SD_LATENCIES_TRP);

    return OK;
}

/************************************************************************
 *    board_systemram_sras2scas_cycles_gt64120_read  
 ************************************************************************/
static UINT32
board_systemram_sras2scas_cycles_gt64120_read(
    void *param,
    void *data )
{
    UINT32 regval;

    GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval );

    switch( REGFIELD( regval, GT_SDRAM_B0_SRAS2SCAS ) )
    {
      case GT_SDRAM_B0_SRAS2SCAS_2 :
        *(UINT32 *)param = 2;
	break;
      case GT_SDRAM_B0_SRAS2SCAS_3 :
        *(UINT32 *)param = 3;
	break;
      default : /* Should not happen */
        return ERROR_SYSCON_UNKNOWN_PARAM;
    }

    return OK;
}


/************************************************************************
 *    board_systemram_sras2scas_cycles_gt64120_write
 ************************************************************************/
static UINT32
board_systemram_sras2scas_cycles_gt64120_write(
    void *param,
    void *data )
{
    UINT32 regval;
  
    /* Read */
    GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval);

    /* Modify */
    regval &= ~GT_SDRAM_B0_SRAS2SCAS_MSK;

    regval |= ( ( ( *(UINT32 *)param <= 2 ) ? 
	           GT_SDRAM_B0_SRAS2SCAS_2 : 
		   GT_SDRAM_B0_SRAS2SCAS_3 ) << 
		      GT_SDRAM_B0_SRAS2SCAS_SHF );

    /* Write */
    GT_W32( sys_nb_base, GT_SDRAM_B0_OFS, regval);

    return OK;
}


/************************************************************************
 *    board_systemram_sras2scas_cycles_sead_read  
 ************************************************************************/
static UINT32
board_systemram_sras2scas_cycles_sead_read(
    void *param,
    void *data )
{
    UINT32 regval;

    regval = REG32(KSEG1(SEAD_SD_LATENCIES));

    *(UINT32 *)param = REGFIELD(regval, SEAD_SD_LATENCIES_TRCD);

    return OK;
}

/************************************************************************
 *    board_systemram_caslat_cycles_gt64120_read
 ************************************************************************/
static UINT32
board_systemram_caslat_cycles_gt64120_read(
    void *param,
    void *data )
{
    UINT32 regval;

    GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval );

    switch( REGFIELD( regval, GT_SDRAM_B0_CASLAT ) )
    {
      case GT_SDRAM_B0_CASLAT_2 :
        *(UINT32 *)param = 2;
	break;
      case GT_SDRAM_B0_CASLAT_3 :
        *(UINT32 *)param = 3;
	break;
      default : /* Should not happen */
        return ERROR_SYSCON_UNKNOWN_PARAM;
    }

    return OK;
}


/************************************************************************
 *    board_systemram_caslat_cycles_sead_read
 ************************************************************************/
static UINT32
board_systemram_caslat_cycles_sead_read(
    void *param,
    void *data )
{