can.txt

用c语言编写的can总线的驱动程序

KICK_DOG 			.macro 			;Watchdog reset macro
LDP			#00E0h
SPLK 		#05555h, WDKEY
SPLK 		#0AAAAh, WDKEY
LDP			#0h
.endm
POINT_PG0 		.macro
LDP			#00h
.endm
POINT_B0 			.macro
LDP			#04h
.endm
POINT_PF1 		.macro
LDP			#0E0h
.endm
POINT_PF2 		.macro
LDP			#0E1h
.endm
POINT_EV 			.macro
LDP			#0E8h
.endm
;Vector address declarations
.global _c_int0
.sect ".vectors"
RSVECT 	B 		_c_int0 			;PM 0 Reset Vector 1
INT1 		B 		PHANTOM 			;PM 2 Int level 1 4
INT2 		B 		PWM_ISR 			;PM 4 Int level 2 5
INT3 		B 		PHANTOM 			;PM 6 Int level 3 6
INT4 		B 		PHANTOM 			;PM 8 Int level 4 7
INT5 		B 		PHANTOM 			;PM A Int level 5 8
INT6 		B 		PHANTOM 			;PM C Int level 6 9
RESERVED 	B 		PHANTOM 			;PM E (Analysis Int) 10
SW_INT8 	B 		PHANTOM 			;PM 10 User S/W int -
SW_INT9 	B 		PHANTOM 			;PM 12 User S/W int -
SW_INT10 	B 		PHANTOM 			;PM 14 User S/W int -
SW_INT11 	B 		PHANTOM 			;PM 16 User S/W int -
SW_INT12 	B 		PHANTOM 			;PM 18 User S/W int -
SW_INT13 	B 		PHANTOM 			;PM 1A User S/W int -
SW_INT14 	B 		PHANTOM 			;PM 1C User S/W int -
SW_INT15 	B 		PHANTOM 			;PM 1E User S/W int -
SW_INT16 	B 		PHANTOM 			;PM 20 User S/W int -
TRAP 		B 		PHANTOM 			;PM 22 Trap vector -
NMI 		B 		PHANTOM 			;PM 24 Non maskable Int 3
EMU_TRAP 	B 		PHANTOM 			;PM 26 Emulator Trap 2
SW_INT20 	B 		PHANTOM 			;PM 28 User S/W int -
SW_INT21 	B 		PHANTOM 			;PM 2A User S/W int -
SW_INT22 	B 		PHANTOM 			;PM 2C User S/W int -
SW_INT23 	B 		PHANTOM 			;PM 2E User S/W int -

;M A I N C O D E - starts here
.text
_c_int0
POINT_PG0
SETC 		INTM 			;Disable interrupts
SPLK 		#0h, IMR 		;Mask all Ints
SPLK 		#0FFh, IFR 		;Clear all Int Flags
CLRC 		SXM 				;Clear Sign Extension Mode
CLRC 		OVM 				;Reset Overflow Mode
CLRC 		CNF 				;Configure Block B0 to Data memory.
POINT_B0
SPLK 		#04h, GPR0 		;Set 0 wait states for XMIF
OUT 			GPR0, WSGR
POINT_PF1
SPLK 		#40C0h,SCSR 	;CLKOUT=CPUCLK
;Comment out if WD is to be active
SPLK 		#006Fh, WDCR 	;Disable WD if VCCP=5V
KICK_DOG
;Activate Lab drive and configure CAN pins
LDPK 		#225
SPLK		#0H,OCRA
SPLK 		#00e0H,OCRB
SPLK 		#2020h, PCDATDIR ;IOPC5 pin high
SPLK 		#1000h,PDDATDIR ;IOPD4 pin low
POINT_PF1
;CAN Initialization
LDP 			#DP_CAN
SPLK 		#1001111111111110b,CANLAM0H ;Set local acceptance mask
SPLK 		#1111111111111111b,CANLAM0L ;1:don't care
SPLK 		#03f7fh,CANIMR ;Set interrupt mask
SPLK 		#0000000000000000b,CANMDER
;bit 0-5 disable each mailbox
SPLK 		#0000000100000000b,CANMCR
;bit 8 CDR: Change data field request
LDP 			#DP_CAN2
SPLK 		#1111111111111111b,CANMSGID0H
;bit 0-15 lower part of extended identifier
SPLK 		#1111111111111011b,CANMSGID0L
LDP 			#DP_CAN
SPLK 		#0000000000000000b,CANMCR
;bit 8 CDR: Change data field request
SPLK 		#0000000000000001b,CANMDER
;bit 0-5 enable mailbox 0
SPLK #0011000000000000b,CANMCR
;bit 12 Change configuration request
W_CCE
BIT 			CANGSR,#0Bh 	;Wait for Change config Enable
BCND 		W_CCE,NTC
LDP 			#DP_CAN
SPLK 		#0000000000000000b,CANBCR2
;bit 0-7 Baud rate prescaler
;bit 8-15 Reserved
SPLK 		#0000010101010111b,CANBCR1
;bit 0-2 TSEG1
;bit 3-6 TSEG2
;bit 7 Sample point setting (1: 3 times, 0: once)
;bit 8-A Synchronization jump width
;bit B Synchronization on falling edge
;bit C-F Reserved
SPLK 		#0010000000000000b,CANMCR
;bit 12 Change configuration request
W_NCCE 
BIT 			CANGSR,#0Bh 	;Wait for Change configuration
BCND 		W_NCCE,TC 		;disable
;Initialize Counter, Step parameters, & AR pointers
SV_PWM
POINT_B0
SPLK 		#STABLE, S_TABLE 	
;Used only to save a cycle
SPLK 		#VF_SLOPE, vf_slope 
;Used later for multiply.
LACC 		#0h 				;Start at 0 deg.
SACL 		ALPHA 			;Clear ANGLE integrator
LACC 		#0h 				;Start at 0 deg.
SACL 		ENTRY_NEW 		;Clear Sine Table Pointer
LACC 		#0h 				;Start at sector 0
SACL 		SECTOR_PTR 		;Init Sector table index pointer
LACC 		#1040 			;Use 41.6 uS period (1040 x 40nS)
;i.e. 24.039 KHz
SACL 		T 				;Init the PWM period
LACC 		#0512 			;Use ~30Hz as Frequency
SACL 		FREQ_SETPT 		;Init the angular speed
SACL 		FREQ_TRGT 		;same speed for Target value
LAR 			AR1, #CMPR1 	;Init Timer Comp reg pointers
LAR 			AR2, #CMPR2
LAR 			AR3, #CMPR3
MAR 			*, 1
;EV Config starts here.
EV_CONFIG
;Configure all I/O pins to I/O function pins
POINT_PF2
SPLK 		#0FFFFh,OCRA
SPLK 		#0h,OCRB
EV_LP
SPLK 		#0C0Ch,PADATDIR ;A3,A2=O/P, A1,A0=I/P, A3,A2=1,1
POINT_B0
SPLK 		#500, mSEC 		;Wait approx 0.5 sec
CALL 		mS_DELAY
POINT_PF2
SPLK 		#00000h,PBDATDIR ;Configure Port B as I/P
;Mask all EV interrupts
;(prevent stray PDPINTs from disabling compare outputs)
POINT_EV 							;DP => EV Registers
SPLK 		#00000h,EVIMRA 	;Mask all Group A interrupt flags
SPLK 		#00000h,EVIMRB 	;Mask all Group B interrupt flags
SPLK		#00000h,EVIMRC 	;Mask all Group C interrupt flags
;Clear EV control registers
SPLK 		#00000h,T1CON 	;GP Timer 1 control
SPLK 		#00000h,T2CON 	;GP Timer 2 control
SPLK 		#00000h,DBTCON 	;Dead band control register
SPLK 		#00000h,COMCON 	;Compare control
SPLK 		#00000h,CAPCON 	;Capture control
SPLK 		#000FFh,CAPFIFO ;Capture FIFO status bits
;Clear all EV interrupts before operation starts
SPLK 		#0FFFFh,EVIFRA 	;Clear all Group A interrupt flags
SPLK 		#0FFFFh,EVIFRB 	;Clear all Group B interrupt flags
SPLK 		#0FFFFh,EVIFRC 	;Clear all Group C interrupt flags
;Setup GP Timers
;Initialize counter registers
SPLK 		#00000h,T1CNT 	;GP Timer 1 counter
SPLK 		#00000h,T2CNT 	;GP Timer 2 counter
;Initialize period registers
POINT_B0
LACC 		T
POINT_EV
SACL 		T1PR 			;GP Timer 1 period
SPLK 		#07FFFh, T2PR 	;Limit counter values to +ve only
;Initialize compare registers
SPLK 		#00100,T1CMPR 	;GP Timer 1 comp value
SPLK 		#00250,T2CMPR 	;GP Timer 2 Comp Value
;Configure GP Timer registers
SPLK 		#0000000001101010b,GPTCON
SPLK 		#1001010101000010b,T2CON 
;Cont Up, /32,
SPLK 		#1001000001000000b,T1CON 
;Asym
;Configure Full Compare registers
POINT_EV
SPLK 		#00100,CMPR1 	;F. Comp U 1 compare value
SPLK 		#00250,CMPR2 	;F. Comp U 2 compare value
SPLK 		#00400,CMPR3 	;F. Comp U 3 compare value
;Start the "Ball rolling" with Timers & Compare units.
POINT_EV
SPLK 		#0000111111101000b,DBTCON
SPLK		#0000011001100110b,ACTR 	
;Full Action Cntl
SPLK 		#0010001000000000b,COMCON 	
;Compare Cntl
SPLK 		#1010001000000000b,COMCON 	
;Compare Cntl
;Enable appropriate Interrupts - EV & DSP core
POINT_EV
SPLK 		#0000001000000000b,EVIMRA ;Enable Underflow Int
SPLK 		#0FFFFh,EVIFRA 	;Clear all Group A interrupt flags
SPLK 		#0FFFFh,EVIFRB 	;Clear all Group B interrupt flags
SPLK 		#0FFFFh,EVIFRC 	;Clear all Group C interrupt flags
POINT_PG0
SPLK 		#0000000000000010b,IMR 
;Enable Int lvl 2 for
SPLK 		#0FFFFh, IFR 	;Clear any pending Ints
CLRC 		INTM 			;Enable global Ints
;Init for Capture
LAR 			AR4, #CAP1FIFO 	;Point to Capture FIFO reg
LAR 			AR5, #BC_BUF_STRT 
;Point to start of BC buffer
MAIN 		B 	MAIN

;Routine Name: P W M _ I S R Routine Type: ISR
;Description:
;Load Timer compare regs with previously calculated Ta, Tb, Tc
;Calculate new Angle (alpha)
;Deduce dx & dy
;Determine current Sector Pointer
;Do Calculated Branch to Sector Subroutine
PWM_ISR:
POINT_EV
SPLK 		#0FFFFh,EVIFRA 	;Clear all Group A interrupt flags
;Calculate Speed Setpoint
POINT_B0
LT 			FREQ_SETPT 		;SPEED_sp
MPY 			#22 				;= FREQ_SETPT x 22
PAC
SACL 		SPEED_sp
LACC 		FREQ_SETPT 		;Load FREQ_SETPT
SACL 		STEP_ANGLE 		;Update new angle increment
;Calculate new Voltage V based on Volts/Freq. profile
PROFILE1 
LACC 		FREQ_SETPT
SUB 			#F1 				;Is Freq.<=F1
BCND 		PROFILE2, GT
LACC 		#Vmin
SACL 		V 				;V is in Q15
B 			NEW_ALPHA
PROFILE2 
LACC 		FREQ_SETPT
SUB 			#F2
BCND 		PROFILE3, GT
LACC 		FREQ_SETPT,4 	;Convert FCV to Q15 format
SACL 		GPR0
LT 			GPR0
MPY 			vf_slope 		;P = vf_slope * FCV
PAC 							;Q13 * Q15 --> Q28
SACH 		V,1 				;convert result to Q13 format
LACC 		V
ADD 			#INTERCEPT 		;INTERCEPT is in Q13
SACL 		V,2 				;result V is in Q15 & <1.0
B 			NEW_ALPHA
PROFILE3 
LACC 		#Vmax
SACL 		V 				;V is in Q15
;Calculate new angle ALPHA
NEW_ALPHA 
LACC 		ENTRY_NEW
SACL 		ENTRY_OLD
LACC 		ALPHA
ADD 			STEP_ANGLE 		;Inc angle.
SACL 		ALPHA
LACC 		ALPHA,8
SACH 		ENTRY_NEW
LACC 		S_TABLE
ADD 			ENTRY_NEW
TBLR 		dy 				;dy=Sin(ALPHA)
LT 			dy 				;dy is in Q15
MPY 			V 				;V is in Q15
PAC 							;P = V * dy
SACH 		dy,1 			;shift 1 to restore Q15 format
LACC 		dy,11 			;scale for 10 bit integer resolution
SACH 		dy 				;Save in Q0 format
LACC 		#0FFh 			;ACC=60 deg
SUB 			ENTRY_NEW
ADD 			S_TABLE
TBLR 		dx 				;dx=Sin(60-ALPHA)
LT 			dx
MPY 			V
PAC 							;P = V * dx
SACH 		dx,1 			;shift 1 to restore Q15 format
LACC 		dx,11 			;scale for 10 bit integer resolution
SACH 		dx 				;Save in Q0 format
;Determine which Sector
LACC 		ENTRY_NEW
SUB 			ENTRY_OLD
BCND 		BRNCH_SR, GEQ 	;If negative need to change sector
;If positive continue
MODIFY_SEC_PTR 
LACC 		SECTOR_PTR
SUB 			#05h 			;Check if at last sector (S6)
BCND 		PISR1,EQ 		;If yes, re-init AR1= 1st Sector (S1)
LACC 		SECTOR_PTR 		;If no, select next Sector (Sn->Sn+1)
ADD 			#01h
SACL 		SECTOR_PTR 		;i.e. inc SECTOR_PTR
B 			BRNCH_SR
PISR1 
SPLK 		#00, SECTOR_PTR ;Reset Sector pointer to 0
BRNCH_SR
LACC 		#SECTOR_TBL
ADD 			SECTOR_PTR
TBLR 		SR_ADDR
LACC 		SR_ADDR
BACC
;Sector 1 calculations - a,b,c --> a,b,c
SECTOR_SR1
LACC 		T 				;Acc = T
SUB 			dx 				;Acc = T-dx
SUB 			dy 				;Acc = T-dx-dy
SFR 							;Acc = Ta = 1/2(T-dx-dy) <A>
SACL 		Ta
ADD 			dx 				;Acc = Tb = dx+Ta <B>
SACL 		Tb
LACC 		T 				;ACC = T
SUB 			Ta 				;ACC = T-Ta
SACL 		Tc 				;ACC = Tc = T-Ta <C>
B 			LOAD_COMPARES
;Sector 2 calculations - a,b,c --> b,a,c & dx <--> dy
SECTOR_SR2
LACC 		T 				;Acc = T
SUB 			dx 				;Acc = T-dx
SUB 			dy 				;Acc = T-dx-dy
SFR 							;Acc = Tb = 1/2(T-dx-dy) <A>
SACL 		Tb
ADD 			dy 				;Acc = Ta = dy+Tb <B>
SACL 		Ta
LACC 		T 				;ACC = T
SUB 			Tb 				;ACC = T-Tb
SACL 		Tc 				;ACC = Tc = T-Tb <C>
B 			LOAD_COMPARES
;Sector 3 calculations - a,b,c --> c,a,b
SECTOR_SR3
LACC 		T 				;Acc = T
SUB 			dx 				;Acc = T-dx
SUB 			dy 				;Acc = T-dx-dy
SFR 							;Acc = Tc = 1/2(T-dx-dy) <A>
SACL 		Tb
ADD 			dx 				;Acc = Ta = dx+Tc <B>
SACL 		Tc
LACC 		T 				;ACC = T
SUB 			Tb 				;ACC = T-Tc
SACL 		Ta 				;ACC = Tb = T-Tc <C>
B 			LOAD_COMPARES
;Sector 4 calculations - a,b,c --> c,b,a & dx <--> dy
SECTOR_SR4
LACC 		T 				;Acc = T
SUB 			dx 				;Acc = T-dx
SUB 			dy 				;Acc = T-dx-dy
SFR 							;Acc = Tc = 1/2(T-dx-dy) <A>
SACL 		Tc
ADD 			dy 				;Acc = Tb = dx+Ta <B>
SACL 		Tb
LACC 		T 				;ACC = T
SUB 			Tc 				;ACC = T-Tc
SACL 		Ta 				;ACC = Ta = T-Tc <C>
B 			LOAD_COMPARES	
;Sector 5 calculations - a,b,c --> b,c,a
SECTOR_SR5
LACC		T 				;Acc = T
SUB 			dx 				;Acc = T-dx
SUB 			dy 				;Acc = T-dx-dy
SFR 							;Acc = Tb = 1/2(T-dx-dy) <A>
SACL 		Tc
ADD 			dx 				;Acc = Tc = dx+Ta <B>