stage.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 20 行

`include "defs.h"

module stage(in00,  in01,  in10,  in11,  in20,  in21,  in30,  in31,  
             sum_enc_bits,  sub_enc_bits,  
             out00,  out01,  out10,  out11,  out20,  out21,  out30,  out31, 
 cmp);

input    [8-1:0] in00,  in01,  in10,  in11,  in20,  in21,  in30,  in31;
input    [4-1:0] sum_enc_bits,  sub_enc_bits;
output   [8-1:0] out00,  out01,  out10,  out11,  out20,  out21,  out30, 
 out31;
output   [4-1:0] cmp;

ACS1_0 state0(in00,  in01,  sum_enc_bits,   out00,  out01,  cmp[0]);
ACS1_1 state1(in10,  in11,  sum_enc_bits,   out10,  out11,  cmp[1]);
ACS2_0 state2(in20,  in21,  sub_enc_bits,   out20,  out21,  cmp[2]);
ACS2_1 state3(in30,  in31,  sub_enc_bits,   out30,  out31,  cmp[3]);

endmodule