res_stage.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 19 行

`include "defs.h"

module res_stage(cmp,  prev00,  prev01,  prev10,  prev11,  prev20, 
 prev21,  prev30,  prev31,  
             nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30, 
 nxt31);

input    [4-1:0]cmp;
input    nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30,  nxt31;
output   prev00,  prev01,  prev10,  prev11,  prev20,  prev21,  prev30, 
 prev31;

res_ACS state0(cmp[0],  prev00,  prev01,  nxt00,  nxt01);
res_ACS state1(cmp[1],  prev10,  prev11,  nxt10,  nxt11);
res_ACS state2(cmp[2],  prev20,  prev21,  nxt20,  nxt21);
res_ACS state3(cmp[3],  prev30,  prev31,  nxt30,  nxt31);

endmodule