ms_res_stage.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 35 行

`include "defs.h"

module MS_res_stage(cmp,  bit_line,  prev00,  prev01,  prev10,  prev11, 
 prev20,  prev21,  prev30,  prev31,  prev40,  prev41,  prev50,  prev51, 
 prev60,  prev61,  prev70,  prev71,  
             nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30,  nxt31, 
 nxt40,  nxt41,  nxt50,  nxt51,  nxt60,  nxt61,  nxt70,  nxt71);

input    [8-1:0]cmp;
input    nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30,  nxt31, 
 nxt40,  nxt41,  nxt50,  nxt51,  nxt60,  nxt61,  nxt70,  nxt71;
output   prev00,  prev01,  prev10,  prev11,  prev20,  prev21,  prev30, 
 prev31,  prev40,  prev41,  prev50,  prev51,  prev60,  prev61,  prev70, 
 prev71;
output   bit_line;

MS_res_ACS1_0 state0(cmp[0],  prev00,  prev01,  nxt00,  nxt01, 
 bit_line);
MS_res_ACS2_0 state1(cmp[1],  prev10,  prev11,  nxt10,  nxt11, 
 bit_line);
MS_res_ACS1_1 state2(cmp[2],  prev20,  prev21,  nxt20,  nxt21, 
 bit_line);
MS_res_ACS2_1 state3(cmp[3],  prev30,  prev31,  nxt30,  nxt31, 
 bit_line);
MS_res_ACS1_1 state4(cmp[4],  prev40,  prev41,  nxt40,  nxt41, 
 bit_line);
MS_res_ACS2_1 state5(cmp[5],  prev50,  prev51,  nxt50,  nxt51, 
 bit_line);
MS_res_ACS1_0 state6(cmp[6],  prev60,  prev61,  nxt60,  nxt61, 
 bit_line);
MS_res_ACS2_0 state7(cmp[7],  prev70,  prev71,  nxt70,  nxt71, 
 bit_line);

endmodule