backtrack.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 35 行

`include "defs.h"

module backtrack(cmp, restart, clk,
             bit_line);

input   [16-1:0] cmp;
input   restart, clk;
output  [3:0] bit_line;

wire    out000, out001, out010, out011, out020, out021, out030, out031,
                 out100, out101, out110, out111, out120, out121, out130, out131,
                 out200, out201, out210, out211, out220, out221, out230, out231,
                 out300, out301, out310, out311, out320, out321, out330, out331;

reg    [7:0]last_out;
always @(posedge clk) last_out = {out300, out301, out310, out311, out320, out321, out330, out331};
reg del_restart;
always @(posedge clk) del_restart = restart;
wire   [7:0]first_in = del_restart == 1 ? {1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0} : last_out;

MS_res_stage  st0(cmp[3:0], bit_line[0],
         out300, out311, out330, out321, out310, out301, out320, out331,
         out000, out001, out010, out011, out020, out021, out030, out031);
MS_res_stage  st1(cmp[7:4], bit_line[1],
         out000, out011, out030, out021, out010, out001, out020, out031,
         out100, out101, out110, out111, out120, out121, out130, out131);
MS_res_stage  st2(cmp[11:8], bit_line[2],
         out100, out111, out130, out121, out110, out101, out120, out131,
         out200, out201, out210, out211, out220, out221, out230, out231);
MS_res_stage  st3(cmp[15:12], bit_line[3],
         out200, out211, out230, out221, out210, out201, out220, out231,
         first_in[7], first_in[6], first_in[5], first_in[4], first_in[3], first_in[2], first_in[1], first_in[0]);

endmodule