in_signal.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 189 行

    @(negedge reset)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = -4;