res_acs.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 19 行

//Actually the node is a CSA and not an ACS.
`include "defs.h"

module res_ACS(compare, traceback_path0, traceback_path1, 
			in_path0, in_path1);

input   compare;
input   in_path0, in_path1;
output  traceback_path0, traceback_path1;

//traceback
wire in_path = in_path0 | in_path1;
wire traceback_path0 = in_path & (compare == 1);
wire traceback_path1 = in_path & (compare == 0);
	
endmodule