block.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 25 行

`include "defs.h"

module block(sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1, cmp, reset, clk);

input            reset, clk;
input   [4-1:0] sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1;
output  [8-1:0] cmp;
wire    [`W-1:0] out000, out001, out010, out011, out020, out021, out030, out031,
                 out100, out101, out110, out111, out120, out121, out130, out131;
reg     [`W-1:0] ns100, ns101, ns110, ns111, ns120, ns121, ns130, ns131;

stage  st0(ns100, ns111, ns130, ns121, ns110, ns101, ns120, ns131,
         sum_enc_bits0, sub_enc_bits0,
         out000, out001, out010, out011, out020, out021, out030, out031, cmp[3:0]);
stage  st1(out000, out011, out030, out021, out010, out001, out020, out031,
         sum_enc_bits1, sub_enc_bits1,
         out100, out101, out110, out111, out120, out121, out130, out131, cmp[7:4]);

       always @(posedge clk)
                {ns100, ns101, ns110, ns111, ns120, ns121, ns130, ns131} = 
                reset ? {8'h64, 56'b0} : 
                {out100, out101, out110, out111, out120, out121, out130, out131};

endmodule