ms_res_stage.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 24 行

`include "defs.h"

module MS_res_stage(cmp,  bit_line,  prev00,  prev01,  prev10,  prev11, 
 prev20,  prev21,  prev30,  prev31,  
             nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30, 
 nxt31);

input    [4-1:0]cmp;
input    nxt00,  nxt01,  nxt10,  nxt11,  nxt20,  nxt21,  nxt30,  nxt31;
output   prev00,  prev01,  prev10,  prev11,  prev20,  prev21,  prev30, 
 prev31;
output   bit_line;

MS_res_ACS1_0 state0(cmp[0],  prev00,  prev01,  nxt00,  nxt01, 
 bit_line);
MS_res_ACS1_1 state1(cmp[1],  prev10,  prev11,  nxt10,  nxt11, 
 bit_line);
MS_res_ACS2_0 state2(cmp[2],  prev20,  prev21,  nxt20,  nxt21, 
 bit_line);
MS_res_ACS2_1 state3(cmp[3],  prev30,  prev31,  nxt30,  nxt31, 
 bit_line);

endmodule