ms_res_acs2_1.v

来自「viterbi译码器的一种fpga实现.是一个cs252 的project的r」· Verilog 代码 · 共 24 行

//Actually the node is a CSA and not an ACS.
`include "defs.h"

module MS_res_ACS2_1(compare,  traceback_path0,  traceback_path1, 
 
			in_path0,  in_path1,  bit_line);

input   compare;
input   in_path0,  in_path1;
output  traceback_path0,  traceback_path1;
output  bit_line;

//traceback
wire in_path = in_path0 | in_path1;
wire traceback_path0 = in_path & (compare == 1);
wire traceback_path1 = in_path & (compare == 0);
	
//wire bit_line = in_path0 ? 0 : (in_path1 ? 1 : 1'bz);
wire bit_line = in_path ? (in_path0 ? 0 : 1) : 1'bz;

endmodule