scalerdef.h

LCD Monitor 部分源码

#define _V_END_L_80                         0x80        // Actuve Region Vertical End LByte
#define _H_START_END_H_81                   0x81        // Actuve Region Horizontal Start/End HByte
#define _H_START_L_82                       0x82        // Actuve Region Horizontal Start LByte
#define _H_END_L_83                         0x83        // Actuve Region Horizontal End LByte
#define _AUTO_PHASE_3_84                    0x84        // Auto Phase Result Register Byte 3
#define _AUTO_PHASE_2_85                    0x85        // Auto Phase Result Register Byte 2
#define _AUTO_PHASE_1_86                    0x86        // Auto Phase Result Register Byte 1
#define _AUTO_PHASE_0_87                    0x87        // Auto Phase Result Register Byte 0
#define _YUV2RGB_CTRL_89                    0x89        // YUV to RGB Control Register
#define _YUV_RGB_COEF_DATA_8A               0x8A        // YUV to RGB Coefficient Data Port
#define _TCON_ADDR_PORT_8B                  0x8B        // TCON Address Port for Embedded TCON Access
#define _TCON_DATA_PORT_8C                  0x8C        // TCON Data Port for Embedded TCON Access
#define _PIN_SHARE_CTRL0_8D                 0x8D        // Pin Share Control Register 0
#define _PIN_SHARE_CTRL1_8E                 0x8E        // Pin Share Control Register 1
#define _PIN_SHARE_CTRL2_8F                 0x8F        // Pin Share Control Register 2

#define _OSD_ADDR_MSB_90                    0x90        // OSD Address MSB
#define _OSD_ADDR_LSB_91                    0x91        // OSD Address LSB
#define _OSD_DATA_PORT_92                   0x92        // OSD Data Port
#define _OSD_SCRAMBLE_93                    0x93        // OSD Scramble
#define _OSD_TEST_94                        0x94        // OSD Test
#define _POWER_ON_RESET_REGULATOR_95        0x95        // Power On Reset and REgulator Voltage
#define _EBD_REGULATOR_VOL_96               0x96        // Embedded Regulator Voltage
#define _HS_SCHMITT_TRIGGER_CTRL_97         0x97        // H Sync Schmitt Trigger Control Register
#define _PLL_DIV_CTRL_98                    0x98        // PLL DIV Control Register
#define _I_CODE_L_99                        0x99        // I Code LByte
#define _I_CODE_M_9A                        0x9A        // I Code MByte
#define _P_CODE_9B                          0x9B        // P Code
#define _PFD_CALIBRATED_RESULTS_9C          0x9C        // PFD Calibrated Result
#define _PE_MEASURE_9D                      0x9D        // Phase Error Measure
#define _PE_MAX_MEASURE_9E                  0x9E        // Phase Error Max MEasure
#define _FAST_PLL_CTRL_9F                   0x9F        // Fast PLL Control Register

#define _FAST_PLL_ISUM_A0                   0xA0        // Fast PLL I_SUM
#define _PLL1_M_A1                          0xA1        // PLL1 M code
#define _PLL1_N_A2                          0xA2        // PLL1 N Code
#define _PLL1_CRNT_A3                       0xA3        // PLL1 Current/Resistor Register
#define _PLL1_WD_A4                         0xA4        // PLL1 Watch Dog Register
#define _PLL2_M_A5                          0xA5        // PLL2 M code
#define _PLL2_N_A6                          0xA6        // PLL2 M code
#define _PLL2_CRNT_A7                       0xA7        // PLL2 Current/Resistor Register
#define _PLL2_WD_A8                         0xA8        // PLL2 Watch Dog Register
#define _PLLDIV_H_A9                        0xA9        // PLL DIV HByte
#define _PLLDIV_L_AA                        0xAA        // PLL DIV LByte
#define _PLLPHASE_CTRL0_AB                  0xAB        // PLL Phase Control Register 0
#define _PLLPHASE_CTRL1_AC                  0xAC        // PLL Phase Control Register 1
#define _PLL2_PHASE_INTERPOLATION_AD        0xAD        // PLL2 Phase Interpolation
#define _DPLL_M_AE                          0xAE        // DPLL M Divider
#define _DPLL_N_AF                          0xAF        // DPLL M Divider

#define _DPLL_CRNT_B0                       0xB0        // DPLL Current/Resistor Register
#define _DPLL_WD_B1                         0xB1        // DPLL Watch Dog Register
#define _MULTI_PLL_CTRL0_B2                 0xB2        // 
#define _MULTI_PLL_CTRL1_B3                 0xB3        // 
#define _PLL_TEST_B4                        0xB4        // Pin3 or Pin4
#define _DCLK_FINE_TUNE_OFFSET_MSB_B5       0xB5        // Display Clock Fine Tune Offset MSB
#define _DCLK_FINE_TUNE_OFFSET_LSB_B6       0xB6        // Display Clock Fine Tune Offset LSB
#define _SPREAD_SPECTRUM_B7                 0xB7        // Spread Spectrum
#define _FIXED_LAST_LINE_MSB_B8             0xB8        // Fixed Last Line MSB
#define _FIXED_LAST_LINE_DVTOTAL_LSB_B9     0xB9        // Fixed Last Line DVTotal LSB
#define _FIXED_LAST_LINE_LENGTH_LSB_BA      0xBA        // Fixed Last Line Length LSB
#define _FIXED_LAST_LINE_CTRL_BB            0xBB        // Fixed Last Line Control Register
#define _TMDS_MEAS_SELECT_BC                0xBC        // TMDS Measure Select
#define _TMDS_MEAS_RESULT0_BD               0xBD        // TMDS Measure Result 0
#define _TMDS_MEAS_RESULT1_BE               0xBE        // TMDS Measure Result 1
#define _TMDS_CTRL_BF                       0xBF        // TMDS Control Register

#define _CRC_OUTPUT_BYTE_2_C0               0xC0        // CRC Output Byte 2
#define _TMDS_OUTPUT_CTRL_C1                0xC1        // TMDS Output Control Register
#define _POWER_ON_OFF_CTRL_C2               0xC2        // TMDS Power On/Off Control Register
#define _ANALOG_COMMON_CTRL0_C3             0xC3        // Analog Common Control Register 0
#define _ANALOG_COMMON_CTRL1_C4             0xC4        // Analog Common Control Register 1
#define _ANALOG_BIAS_CTRL_C5                0xC5        // Analog Bias Control Register
#define _ANALOG_COMMON_CTRL2_C6             0xC6        // Analog Common Control Register 2
#define _Z0_CALIBRATION_CTRL_C7             0xC7        // Z0 Calibration Control Register
#define _CLOCK_PLL_SETTING_C8               0xC8        // Clock PLL Setting
#define _RGB_PLL_SETTING_C9                 0xC9        // R/G/B PLL Setting
#define _WATCHDOG_CTRL0_CA                  0xCA        // Watch Dog Control 0
#define _CDR_CTRL0_CB                       0xCB        // CDR Control Register 0
#define _CDR_CTRL1_CC                       0xCC        // CDR Control Register 1
#define _CDR_CTRL2_CD                       0xCD        // CDR Control Register 2
#define _UP_DOWN_ADJUSTING0_CE              0xCE        // Up/Down Adjusting 0
#define _UP_DOWN_ADJUSTING1_CF              0xCF        // Up/Down Adjusting 1

#define _UP_DOWN_ADJUSTING2_D0              0xD0        // Up/Down Adjusting 2
#define _UP_DOWN_CTRL0_D1                   0xD1        // Up/Down Control Register 0
#define _UP_DOWN_CTRL1_D2                   0xD2        // Up/Down Control Register 1
#define _UP_DOWN_CTRL2_D3                   0xD3        // Up/Down Control Register 2
#define _UP_DOWN_CTRL3_D4                   0xD4        // Up/Down Control Register 3
#define _HDCP_CTRL_D5                       0xD5        // HDCP Control Register
#define _DEVICE_KEY_ACCESS_PORT_D6          0xD6        // Device Key Access Port
#define _DEVICE_KEY_BIST_PATTERN_D7         0xD7        // Device Key BIST Pattern
#define _HDCP_ADDR_PORT_D8                  0xD8        // HDCP Address Port
#define _HDCP_DATA_PORT_D9                  0xD9        // HDCP Data Port
#define _WATCHDOG_CTRL1_DA                  0xDA        // Watch Dog Control 1
#define _MACRO_VISION_CTRL_DB               0xDB        // Macro Vision Control Register
#define _ADC_RGB_CTRL_DC                    0xDC        // ADC RGB Control Register
#define _ADC_RED_CTRL_DD                    0xDD        // ADC Red Control Register
#define _ADC_GRN_CTRL_DE                    0xDE        // ADC Green Control Register
#define _ADC_BLU_CTRL_DF                    0xDF        // ADC Blue Control Register

#define _RED_GAIN_E0                        0xE0        // ADC Red Gain
#define _GRN_GAIN_E1                        0xE1        // ADC Green Gain
#define _BLU_GAIN_E2                        0xE2        // ADC Blue Gain
#define _RED_OFFSET_E3                      0xE3        // ADC Red Offset
#define _GRN_OFFSET_E4                      0xE4        // ADC Green Offset
#define _BLU_OFFSET_E5                      0xE5        // ADC Blue Offset
#define _SOG0_CTRL_E6                       0xE6        // SOG0 Control Register
#define _SOG1_CTRL_E7                       0xE7        // SOG1 Control Register
#define _ADC_POWER_CTRL_E8                  0xE8        // ADC Power Control Register
#define _ADC_CLOCK_E9                       0xE9        // ADC Clock
#define _ADC_TEST_EA                        0xEA        // ADC Test
#define _ADC_IBIAS2_EB                      0xEB        // ADC IBIAS2
#define _ADC_VBIAS0_EC                      0xEC        // ADC VBIAS0
#define _ADC_VBIAS1_ED                      0xED        // ADC VBIAS1
#define _PTNPOS_H_EE                        0xEE        // PTNPOS HByte
#define _PTNPOS_V_L_EF                      0xEF        // PTNPOS Vertical LByte

#define _PTNPOS_H_L_F0                      0xF0        // PTNPOS Horizontal LByte
#define _PTNRD_F1                           0xF1        // PTNRD
#define _OP_CRC_CTRL_F2                     0xF2        // Output CRC Control Register
#define _OP_CRC_CHECKSUM_F3                 0xF3        // Output CRC Checksum
#define _DDC_SET_SLAVE_F4                   0xF4        // DDC Set Slave Address
#define _DDC_SUB_IN_F5                      0xF5        // DDC Sub Address Received
#define _DDC_DATA_IN_F6                     0xF6        // DDC Data Received
#define _DDC_CTRL_F7                        0xF7        // DDC Control Register
#define _DDC_STATUS_F8                      0xF8        // DDC Status
#define _DDC_IRQ_CTRL_F9                    0xF9        // DDC IRQ Control Register
#define _DDC_ENABLE_FA                      0xFA        // DDC Channel Enable Control Register
#define _DDC_INDEX_FB                       0xFB        // DDC SRAM R/W Index Register
#define _DDC_ACCESS_PORT_FC                 0xFC        // DDC Channel Access Port
#define _DDC_DVI_ENABLE_FD                  0xFD        // DDC DVI Channel Enable Control Register
#define _DDC_DVI_INDEX_FE                   0xFE        // DDC DVI SRAM R/W Index Register
#define _DDC_DVI_ACCESS_PORT_FF             0xFF        // DDC DVI Channel Access Port



#define _LVDS_CTRL0_78                      0x78        // 
#define _LVDS_CTRL1_79                      0x79        // 
#define _LVDS_CTRL2_7A                      0x7A        // 
#define _LVDS_CTRL3_7B                      0x7B        // 
#define _LVDS_CTRL4_7C                      0x7C        // 
#define _LVDS_CTRL5_7D                      0x7D        //