scalerdef.h

LCD Monitor 部分源码

//----------------------------------------------------------------------------------------------------
// ID Code      : ScalerDef.h No.0000
// Update Note  : 
//
//----------------------------------------------------------------------------------------------------

//--------------------------------------------------
// Definitions of RTD2323 Control Register Address
//--------------------------------------------------
#define _ID_REG_00                          0x00        // ID Code Register
#define _HOST_CTRL_01                       0x01        // Host Control Register
#define _STATUS0_02                         0x02        // Status0 Register
#define _STATUS1_03                         0x03        // Status1 Register
#define _IRQ_CTRL_04                        0x04        // IRQ Control Register
#define _VGIP_CTRL_05                       0x05        // Video Graphic Input Port(VGIP) Control Register
#define _VGIP_SIGINV_06                     0x06        // Input Control Signal Inverted Register
#define _VGIP_DELAY_CTRL_07                 0x07        // VGIP Delay Control Register
#define _VGIP_ODD_CTRL_08                   0x08        // VGIP Odd Control Register
#define _IPH_ACT_STA_H_09                   0x09        // Input Horizontal Active Start HByte
#define _IPH_ACT_STA_L_0A                   0x0A        // Input Horizontal Active Start LByte
#define _IPH_ACT_WID_H_0B                   0x0B        // Input Horizontal Active Width HByte
#define _IPH_ACT_WID_L_0C                   0x0C        // Input Horizontal Active Width LByte
#define _IPV_ACT_STA_H_0D                   0x0D        // Input Vertical Active Start HByte
#define _IPV_ACT_STA_L_0E                   0x0E        // Input Vertical Active Start LByte
#define _IPV_ACT_LEN_H_0F                   0x0F        // Input Vertical Active Length HByte

#define _IPV_ACT_LEN_L_10                   0x10        // Input Vertical Active Length LByte
#define _IVS_DELAY_11                       0x11        // Internal Input Vertical Sync(VS) Delay Control Register
#define _IHS_DELAY_12                       0x12        // Internal Input Horizontal Sync(HS) Delay Control Register
#define _VGIP_HV_DELAY_13                   0x13        // VGIP HS/VS Delay
#define _DWRWL_H_BSU_14                     0x14        // Display Window Read Width/Length HByte Before Scaling Up
#define _DWRW_L_BSU_15                      0x15        // Display Window Read Width LByte Before Scaling Up
#define _DWRL_L_BSU_16                      0x16        // Display Window Read Length LByte Before Scaling Up
#define _DIGITAL_FILTER_CTRL_17             0x17        // Digital Filter Control Register
#define _DIGITAL_FILTER_PORT_18             0x18        // Digital Filter Port
#define _SCALE_CTRL_19                      0x19        // Scale Control Register
#define _SF_ACCESS_PORT_1A                  0x1A        // Scaling Factor Access Port
#define _SF_DATA_PORT_1B                    0x1B        // Scaling Factor Data Port
#define _FILTER_CTRL_1C                     0x1C        // Filter Control Register
#define _FILTER_PORT_1D                     0x1D        // User Defined Filter Access Port
#define _OSD_REFERENCE_DEN_1E               0x1E        // 
#define _NEW_DV_CTRL_1F                     0x1F        // 

#define _NEW_DV_DLY_20                      0x20        // 
#define _RESERVED_21                        0x21        // Reserved 21
#define _SCALE_DOWN_CTRL_22                 0x22        // Scale Down Control Register
#define _H_SCALE_DOWN_H_23                  0x23        // Horizontal Scale Down Factor Register
#define _H_SCALE_DOWN_M_24                  0x24        // Horizontal Scale Down Factor Register
#define _H_SCALE_DOWN_L_25                  0x25        // Horizontal Scale Down Factor Register
#define _V_SCALE_DOWN_H_26                  0x26        // Vertical Scale Down Factor Register
#define _V_SCALE_DOWN_L_27                  0x27        // Vertical Scale Down Factor Register
#define _VDISP_CTRL_28                      0x28        // Video Display Control Register
#define _VDISP_SIGINV_29                    0x29        // Display Control Signal Inverted Register
#define _DH_TOTAL_H_2A                      0x2A        // Display Horizontal Total Pixels HByte
#define _DH_TOTAL_L_2B                      0x2B        // Display Horizontal Total Pixels LByte
#define _DHS_END_2C                         0x2C        // Display Horizontal Sync End Pixels
#define _DH_BKGD_STA_H_2D                   0x2D        // Display Horizontal Background Start HByte
#define _DH_BKGD_STA_L_2E                   0x2E        // Display Horizontal Background Start LByte
#define _DH_ACT_STA_H_2F                    0x2F        // Display Horizontal Active Start HByte

#define _DH_ACT_STA_L_30                    0x30        // Display Horizontal Active Start LByte
#define _DH_ACT_END_H_31                    0x31        // Display Horizontal Active End HByte
#define _DH_ACT_END_L_32                    0x32        // Display Horizontal Active End LByte
#define _DH_BKGD_END_H_33                   0x33        // Display Horizontal Background End HByte
#define _DH_BKGD_END_L_34                   0x34        // Display Horizontal Background End LByte
#define _DV_TOTAL_H_35                      0x35        // Display Vertical Total Lines HByte 
#define _DV_TOTAL_L_36                      0x36        // Display Vertical Total Lines LByte 
#define _DVS_END_37                         0x37        // Display Vertical Sync End Lines
#define _DV_BKGD_STA_H_38                   0x38        // Display Vertical Background Start HByte
#define _DV_BKGD_STA_L_39                   0x39        // Display Vertical Background Start LByte
#define _DV_ACT_STA_H_3A                    0x3A        // Display Vertical Active Start HByte
#define _DV_ACT_STA_L_3B                    0x3B        // Display Vertical Active Start LByte
#define _DV_ACT_END_H_3C                    0x3C        // Display Vertical Active End HByte
#define _DV_ACT_END_L_3D                    0x3D        // Display Vertical Active End LByte
#define _DV_BKGD_END_H_3E                   0x3E        // Display Vertical Background End HByte
#define _DV_BKGD_END_L_3F                   0x3F        // Display Vertical Background End LByte

#define _IVS2DVS_DELAY_LINES_40             0x40        // IVS to DVS Delay Lines
#define _IV_DV_DELAY_CLK_ODD_41             0x41        // Frame Sync Delay Fine Tuning ODD
#define _IV_DV_DELAY_CLK_EVEN_42            0x42        // Frame Sync Delay Fine Tuning EVEN
#define _FS_DELAY_FINE_TUNING_43            0x43        // Frame Sync Delay Fine Tuning Control Register
#define _LAST_LINE_H_44                     0x44        // Last Line HByte
#define _LAST_LINE_L_45                     0x45        // Last Line LByte
#define _DISP_TIMING_46                     0x46        // Display Clock Fine Tuning Register
#define _SYNC_SELECT_47                     0x47        // Sync Select Control Register
#define _SYNC_INVERT_48                     0x48        // Sync Invert Control Register
#define _SYNC_CTRL_49                       0x49        // Sync Processor Control Register
#define _DETECT_HSYNC_PERIOD_MSB_4A         0x4A        // Detect Horizontal Sync Period Counted by Crystal Clock MSB
#define _DETECT_HSYNC_PERIOD_LSB_4B         0x4B        // Detect Horizontal Sync Period Counted by Crystal Clock LSB
#define _VSYNC_COUNTER_LEVEL_MSB_4C         0x4C        // Vertical Sync Counter Level MSB
#define _VSYNC_COUNTER_LEVEL_LSB_4D         0x4D        // Vertical Sync Counter Level LSB
#define _SYNC_POLARITY_PERIOD_COUNT_4E      0x4E        // Sync Polarity Period Count Number
#define _STABLE_COUNT_4F                    0x4F        // Stable Count

#define _STABLE_PERIOD_H_50                 0x50        // Stable Period HByte
#define _STABLE_PERIOD_L_51                 0x51        // Stable Period LByte
#define _MEAS_HS_PERIOD_H_52                0x52        // HSync Period Measured Result HByte
#define _MEAS_HS_PERIOD_L_53                0x53        // HSync Period Measured Result LByte
#define _MEAS_VS_PERIOD_H_54                0x54        // VSync Period Measured Result HByte
#define _MEAS_VS_PERIOD_L_55                0x55        // VSync Period Measured Result LByte
#define _MEAS_HS_VS_HIGH_PERIOD_H_56        0x56        // HSync and VSync High Period Measured Results HByte
#define _MEAS_HS_HIGH_PERIOD_L_57           0x57        // HSync High Period Measured Results LByte
#define _MEAS_VS_HIGH_PERIOD_L_58           0x58        // VSync High Period Measured Results LByte
#define _MEAS_ACTIVE_REGION_59              0x59        // Active Region Measured by Crystal Clock
#define _CLAMP_START_5A                     0x5A        // Clamp Signal Output Start
#define _CLAMP_END_5B                       0x5B        // Clamp Signal Output End
#define _CLAMP_CTRL0_5C                     0x5C        // Clamp Signal Control Register 0
#define _CLAMP_CTRL1_5D                     0x5D        // Clamp Signal Control Register 1
#define _COLOR_CTRL_5E                      0x5E        // Color Processor Control Register
#define _SRGB_ACCESS_PORT_5F                0x5F        // sRGB Access Port

#define _BRI_RED_COE_60                     0x60        // Brightness Red Coefficient
#define _BRI_GRN_COE_61                     0x61        // Brightness Green Coefficient
#define _BRI_BLU_COE_62                     0x62        // Brightness Blue Coefficient
#define _CTS_RED_COE_63                     0x63        // Contrast Red Coefficient
#define _CTS_GRN_COE_64                     0x64        // Contrast Green Coefficient
#define _CTS_BLU_COE_65                     0x65        // Contrast Blue Coefficient
#define _GAMMA_PORT_66                      0x66        // Gamma Access Port
#define _GAMMA_CTRL_67                      0x67        // Gamma Control Register
#define _GAMMA_BIST_68                      0x68        // Gamma BIST Control Register
#define _DITHERING_SEQUENCE_TABLE_69        0x69        // Dithering Sequence Table
#define _DITHERING_TABLE_ACCESS_PORT_6A     0x6A        // Dithering Table Access Port
#define _DITHERING_CTRL_6B                  0x6B        // Dithering Control Register
#define _OVERLAY_CTRL_6C                    0x6C        // Overlay Display Control Register
#define _BGND_COLOR_CTRL_6D                 0x6D        // Background Color Control Register
#define _OVERLAY_LUT_ADDR_6E                0x6E        // Overlay Look Up Table (LUT) Address
#define _COLOR_LUT_PORT_6F                  0x6F        // Color LUT Access Port

#define _H_BOUNDARY_H_70                    0x70        // Horizontal Start/End Boundary HByte
#define _H_BOUNDARY_STA_L_71                0x71        // Horizontal Start Boundary HByte
#define _H_BOUNDARY_END_L_72                0x72        // Horizontal End Boundary HByte
#define _V_BOUNDARY_H_73                    0x73        // Vertical Start/End Boundary HByte
#define _V_BOUNDARY_STA_L_74                0x74        // Vertical Start Boundary LByte
#define _V_BOUNDARY_END_L_75                0x75        // Vertical End Boundary LByte
#define _RED_NOISE_MARGIN_76                0x76        // Red Noise Margin Control Register
#define _GRN_NOISE_MARGIN_77                0x77        // Green Noise Margin Control Register
#define _BLU_NOISE_MARGIN_78                0x78        // Blue Noise Margin Control Register
#define _DIFF_THRESHOLD_79                  0x79        // Difference Threshold
#define _AUTO_ADJ_CTRL0_7A                  0x7A        // Auto Adjusting Control Register 0
#define _HW_AUTO_PHASE_CTRL0_7B             0x7B        // Hardware Auto Phase Control Register 0
#define _HW_AUTO_PHASE_CTRL1_7C             0x7C        // Hardware Auto Phase Control Register 1
#define _AUTO_ADJ_CTRL1_7D                  0x7D        // Auto Adjusting Control Register 1
#define _V_START_END_H_7E                   0x7E        // Actuve Region Vertical Start/End HByte
#define _V_START_L_7F                       0x7F        // Actuve Region Vertical Start LByte