pnl_lvds17.h

LCD Monitor 部分源码

#define HINT_POS_LEFT                   0x09
#define HINT_POS_RIGHT                  0xad
#define HINT_POS_TOP                    0x03
#define HINT_POS_BOTTOM                 0xab

#define _OSD_HPOSITION_OFFSET           ((_DH_ACT_STA_POS / 4) + 0)
#define _OSD_VPOSITION_OFFSET           ((_DV_ACT_STA_POS / 5) + 0)
//--------------------------------------------------
#define _PANEL_LVDS                     0
#define _PANEL_RSDS                     1
#define _PANEL_TTL                      2

#define _OUTPUT_BUS                      _PANEL_LVDS
//--------------------------------------------------
#define _DISP_24_BIT                    (0 << 7)
#define _DISP_18_BIT                    (1 << 7)

#define _DISP_BIT                        _DISP_24_BIT
//--------------------------------------------------
#define _DISP_EO_SWAP                   (1 << 6)
#define _DISP_RB_SWAP                   0//(1 << 5)
#define _DISP_ML_SWAP                   0//(1 << 4)
//--------------------------------------------------
#define _DISP_SINGLE_PORT               (0 << 3)
#define _DISP_DOUBLE_PORT               (1 << 3)

#define _DISPLAY_PORT                    _DISP_DOUBLE_PORT
//--------------------------------------------------
#define _RSDS_GC_SWAP                   0//(1 << 2)
#define _RSDS_HL_SWAP                   0//(1 << 1)
#define _RSDS_PN_SWAP                   0//(1 << 0)
//--------------------------------------------------
#define _DISP_WID                        1280
#define _DISP_LEN                        1024

#define _DH_ACT_STA_POS                  32
#define _DH_ACT_END_POS                  (_DISP_WID + _DH_ACT_STA_POS)

#define _DV_ACT_STA_POS                  12
#define _DV_ACT_END_POS                  (_DISP_LEN + _DV_ACT_STA_POS)

//--------------------------------------------------
#define LVDS_MAP1                       0x00
#define LVDS_MAP2                       0x01

#define LVDS_MAP                        LVDS_MAP1
//--------------------------------------------------
#define VIDEO_60_DH_TOTAL               0x56e//0x5b0
#define VIDEO_50_DH_TOTAL               0x578//0x5b0
#define NTSC_DCLK                       95600
#define PAL_DCLK                        80570
//--------------------------------------------------
#define STD_DH_TOTAL                    1380//1440//1463//1408
#define MAX_DH_TOTAL                    2044
#define MIN_DH_TOTAL                    1380

#define STD_DV_TOTAL                    1072
#define MAX_DV_TOTAL                    1272
#define MIN_DV_TOTAL                    1034

#define STD_PIXCEL_CLOCK                135
#define MAX_PIXCEL_CLOCK                170
#define MIN_PIXCEL_CLOCK                100

#define HSYNC_WIDTH                     16
#define VSYNC_HEIGHT                    3
//--------------------------------------------------
#define _DISP_INFO_BY_MODE                _OFF
//--------------------------------------------------
// Definitions for First DHS Masking
//--------------------------------------------------
#define _DHS_MASK                       0//(1 << 7)


//--------------------------------------------------
// Definitions for Display Signal
//--------------------------------------------------
#define _DVS_INVERT                     (_DISABLE << 2)
#define _DHS_INVERT                     (_DISABLE << 1)
#define _DEN_INVERT                     (_DISABLE)

#define _DISPLAY_INVERT                 (_DVS_INVERT | _DHS_INVERT | _DEN_INVERT)


//--------------------------------------------------
// Definitions for Display Control
//--------------------------------------------------
#define _DISPLAY_CTRL                   (_DHS_MASK | _DISPLAY_INVERT)

//--------------------------------------------------
// Support Timing
//--------------------------------------------------
#define _H_FREQ_MAX                     930             // Unit in 0.1 kHZ
#define _H_FREQ_MIN                     200             // Unit in 0.1 kHZ
#define _V_FREQ_MAX                     890             // Unit in 0.1 HZ
#define _V_FREQ_MIN                     490             // Unit in 0.1 HZ

#ifdef __MAIN__
//--------------------------------------------------
// Display Interface Initial
//--------------------------------------------------
BYTE code tTTL_INITIAL[] =
{
    #if(_OUTPUT_BUS == _PANEL_TTL)    
    
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x00,0x00,

    #endif

    _END
};
//--------------------------------------------------
BYTE code tLVDS_INITIAL[] =
{
#if(_OUTPUT_BUS == _PANEL_LVDS)

#if(_SCALER_TYPE == _RTD2323)

    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x00,0x02,
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x01,0x04,
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             _LVDS_CTRL0_78,
    9,  _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0xf0,0x04,0x13,0x12 | LVDS_MAP,0x80,0x80,

#elif((_SCALER_TYPE == _RTD2023L) || (_SCALER_TYPE == _RTD2023S))

    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x00,0x02,
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x01,0x14,
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             _LVDS_CTRL0_78,
    9,  _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0xf0,0x17,0x05,0x1c | LVDS_MAP,0x80,0x80,

#endif

#endif

    _END
};
//--------------------------------------------------
BYTE code tRSDS_INITIAL[] =
{
    #if(_OUTPUT_BUS == _PANEL_RSDS)

    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x00,0x83,
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x01,0x14,
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x06,0x06,
    5,  _AUTOINC,       _TCON_ADDR_PORT_8B,             0x07,0x7f,

    // YCLK TCON0
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x08,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0c,0xf4,0x21,0x94,0x80,

    // FXDIO TCON1
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x10,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0c,0xab,0x22,0xaf,0x80,

    // YOE TCON3 
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x20,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0c,0x94,0x52,0x14,0x80,

    // POL TCON7
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x40,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0d,0x00,0x00,0x01,0x88,

    // BXDIO TCON11
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x60,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0c,0xab,0x22,0xaf,0x80,

    // YDIO TCON12
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x68,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x00,0x0e,0xd0,0x33,0xd7,0x88,

    // XSTB TCON13
    4,  _NON_AUTOINC,   _TCON_ADDR_PORT_8B,             0x70,
    10, _NON_AUTOINC,   _TCON_DATA_PORT_8C,             0x0c,0x40,0x0c,0x35,0x22,0xac,0x80,
    #endif

    _END
};
//--------------------------------------------------
// EDID Table
//--------------------------------------------------
BYTE code tEDID_TABLE_VGA[] =
{
    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x4a,0x8b,0x00,0x00,0x01,0x01,0x01,0x01,
    0x1e,0x0c,0x01,0x01,0x0e,0x24,0x1b,0x78,0xe8,0x8a,0x01,0x9a,0x58,0x52,0x8b,0x28,
    0x1e,0x50,0x54,0xff,0xff,0x80,0x61,0x40,0x61,0x4f,0x61,0x59,0x71,0x4f,0x81,0x40,
    0x81,0x59,0x81,0x99,0xa9,0x40,0x00,0x00,0x00,0xfc,0x00,0x31,0x37,0x27,0x27,0x20,
    0x4c,0x43,0x44,0x0a,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfc,0x00,0x4d,0x6f,0x6e,
    0x69,0x74,0x6f,0x72,0x0a,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfd,0x00,0x2b,
    0x55,0x14,0x5c,0x0e,0x00,0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xff,
    0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xbd,
};
//--------------------------------------------------
BYTE code tEDID_TABLE_DVI[] =
{
    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
    0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,
    0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
    0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
    0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
    0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
    0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
    0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
};
//--------------------------------------------------
code PanelType Panel =
{        
        _OUTPUT_BUS,                                        // Panel Style
                                                           
        _DISPLAY_PORT | _DISP_BIT |                            // Panel Configuration
        _DISP_EO_SWAP | _DISP_RB_SWAP | _DISP_ML_SWAP | 
        _DISPLAY_PORT | 
        _RSDS_GC_SWAP | _RSDS_HL_SWAP | _RSDS_PN_SWAP,

        _DH_ACT_STA_POS,                                         // Display Horizontal Start Position
        _DISP_WID,                                               // Display Horizontal Width
        _DH_ACT_END_POS,                                         // Display Horizontal End Position

        STD_DH_TOTAL,                                           // Display Horizontal Total Clock Number in One Display Line
        MAX_DH_TOTAL,                                           // Maxinum Display Horizontal Total Clock Number in One Display Line
        MIN_DH_TOTAL,                                           // Mininum Display Horizontal Total Clock Number in One Display Line

        _DV_ACT_STA_POS,                                         // Display Vertical Start Position
        _DISP_LEN,                                               // Display Vertical Height
        _DV_ACT_END_POS,                                         // Display Vertical End Position

        STD_DV_TOTAL,                                           // Display Vertical Total Line Number in One Frame
        MAX_DV_TOTAL,                                           // Maxinum Display Vertical Total Line Number in One Frame
        MIN_DV_TOTAL,                                           // Mininum Display Vertical Total Line Number in One Frame

        HSYNC_WIDTH,                                            // Display H Sync Width
        VSYNC_HEIGHT,                                           // Display V Sync Height

        STD_PIXCEL_CLOCK,                                       // Typical Pixel Clock in MHz
        MAX_PIXCEL_CLOCK,                                       // Maxinum Pixel Clock in MHz
        MIN_PIXCEL_CLOCK                                        // Mininum Pixel Clock in MHz
};
//--------------------------------------------------
WORD code tVIDEO_TABLE_INPUT_INFO[][5] =
{
    // IHTotal, IHStart, IHWidth, IVStart, IVHeight
    {    864,     25,     666,     6,     278 },  // 50HZ 
    {    858,     39,     640,     14,    234 },  // 60HZ
};

//--------------------------------------------------
unsigned int code tModeLimitTable[] =                //limit modem
{
	0,
    _MODE_1280x1024_60HZ,
	
};
//--------------------------------------------------
#else

extern BYTE code tTTL_INITIAL[];
extern BYTE code tLVDS_INITIAL[];
extern BYTE code tRSDS_INITIAL[];

extern BYTE code tEDID_TABLE_VGA[];
extern BYTE code tEDID_TABLE_DVI[];

WORD code tVIDEO_TABLE_INPUT_INFO[][5];
extern unsigned int code tModeLimitTable[];
extern code PanelType Panel;
#endif
//-------------------------------------------------------------