myproject.edf

这是一个计数器原理图

(edif MyProject_PrjFpg
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
     (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2006 3 5 22 51 11)
      (program "Design Explorer DXP - EDIF For PCB"
        (version "1.0.0")
      )
      (author "EDIF For PCB")
    )
  )

  (library COMPONENT_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell FJKC
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port C   (direction INPUT))
          (port CLR (direction INPUT))
          (port J   (direction INPUT))
          (port K   (direction INPUT))
          (port Q   (direction OUTPUT))
        )
      )
    )
    (cell INV
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell OR2B2
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O  (direction OUTPUT))
        )
      )
    )
    (cell SR4CLED
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port C    (direction INPUT))
          (port CE   (direction INPUT))
          (port CLR  (direction INPUT))
          (port D0   (direction INPUT))
          (port D1   (direction INPUT))
          (port D2   (direction INPUT))
          (port D3   (direction INPUT))
          (port L    (direction INPUT))
          (port LEFT (direction INPUT))
          (port Q0   (direction OUTPUT))
          (port Q1   (direction OUTPUT))
          (port Q2   (direction OUTPUT))
          (port Q3   (direction OUTPUT))
          (port SLI  (direction INPUT))
          (port SRI  (direction INPUT))
        )
      )
    )
  )
  (library SHEET_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell Counter_SchDoc
      (cellType generic)
      (view netListView
        (viewType netlist)
        (interface
        )
        (contents
          (Instance U1
            (viewRef NetlistView
              (cellRef SR4CLED
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "SR4CLED" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "4-Bit Shift Register with Clock Enable and Asynchronous Clear" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "SR4CLED" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "4-Bit Shift Register with Clock Enable and Asynchronous Clear" ))
            (Property UniqueId (String "\AUCOKELN" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "0" ))
          )
          (Instance U2
            (viewRef NetlistView
              (cellRef OR2B2
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "OR2B2" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "2-Input OR Gate with Two Inverted Inputs" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "OR2B2" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "2-Input OR Gate with Two Inverted Inputs" ))
            (Property UniqueId (String "\FKHYHDEP" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "1" ))
          )
          (Instance U3
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "\PGCESIXX" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "2" ))
          )
          (Instance U4
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "\XIGRNFKQ" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "3" ))
          )
          (Instance U5
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "\WIEYTFOS" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "4" ))
          )
          (Instance U6
            (viewRef NetlistView
              (cellRef INV