counter.edf

这是一个计数器原理图

(edif Design_Counter_SchDoc
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
     (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2006 3 5 22 51 24)
      (program "Design Explorer DXP - EDIF For PCB"
        (version "1.0.0")
      )
      (author "EDIF For PCB")
    )
  )

  (library COMPONENT_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell FJKC
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port C   (direction INPUT))
          (port CLR (direction INPUT))
          (port J   (direction INPUT))
          (port K   (direction INPUT))
          (port Q   (direction OUTPUT))
        )
      )
    )
    (cell INV
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell OR2B2
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O  (direction OUTPUT))
        )
      )
    )
    (cell SR4CLED
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port C    (direction INPUT))
          (port CE   (direction INPUT))
          (port CLR  (direction INPUT))
          (port D0   (direction INPUT))
          (port D1   (direction INPUT))
          (port D2   (direction INPUT))
          (port D3   (direction INPUT))
          (port L    (direction INPUT))
          (port LEFT (direction INPUT))
          (port Q0   (direction OUTPUT))
          (port Q1   (direction OUTPUT))
          (port Q2   (direction OUTPUT))
          (port Q3   (direction OUTPUT))
          (port SLI  (direction INPUT))
          (port SRI  (direction INPUT))
        )
      )
    )
  )
  (library SHEET_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell Counter_SchDoc
      (cellType generic)
      (view netListView
        (viewType netlist)
        (interface
          (port CLK   (direction INPUT))
          (port LEFT  (direction INPUT))
          (port LOAD  (direction INPUT))
          (port Q0    (direction OUTPUT))
          (port Q1    (direction OUTPUT))
          (port Q2    (direction OUTPUT))
          (port Q3    (direction OUTPUT))
          (port RIGHT (direction INPUT))
          (port STOP  (direction INPUT))
        )
        (contents
          (Instance U1
            (viewRef NetlistView
              (cellRef SR4CLED
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "SR4CLED" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "4-Bit Shift Register with Clock Enable and Asynchronous Clear" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "SR4CLED" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "4-Bit Shift Register with Clock Enable and Asynchronous Clear" ))
            (Property UniqueId (String "$$$\AUCOKELN" ))
          )
          (Instance U2
            (viewRef NetlistView
              (cellRef OR2B2
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "OR2B2" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "2-Input OR Gate with Two Inverted Inputs" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "OR2B2" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "2-Input OR Gate with Two Inverted Inputs" ))
            (Property UniqueId (String "$$$\FKHYHDEP" ))
          )
          (Instance U3
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "$$$\PGCESIXX" ))
          )
          (Instance U4
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "$$$\XIGRNFKQ" ))
          )
          (Instance U5
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "$$$\WIEYTFOS" ))
          )
          (Instance U6
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "$$$\DRPTTIOR" ))
          )
          (Instance U7
            (viewRef NetlistView
              (cellRef INV
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "INV" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "Inverter" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "INV" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "Inverter" ))
            (Property UniqueId (String "$$$\JRTMIDUJ" ))
          )
          (Instance U8
            (viewRef NetlistView
              (cellRef FJKC
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "FJKC" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "J-K Flip-Flop with Asynchronous Clear" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "FJKC" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "J-K Flip-Flop with Asynchronous Clear" ))
            (Property UniqueId (String "$$$\RVDYWOHP" ))
          )
          (Instance U9
            (viewRef NetlistView
              (cellRef FJKC
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "FJKC" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Datasheet (String "Latest Revision: 1999" ))
            (Property Description (String "J-K Flip-Flop with Asynchronous Clear" ))
            (Property FPGAVendor (String "Xilinx" ))
            (Property (rename Library_Name "Library Name") (String "Xilinx Spartan-IIE FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "FJKC" ))
            (Property Published (String "7-3-2002" ))
            (Property Publisher (String "Altium Hobart Technology Centre" ))
            (Property Revision (String "9/15/2003" ))
            (Property Description (String "J-K Flip-Flop with Asynchronous Clear" ))
            (Property UniqueId (String "$$$\UFBJVDFI" ))
          )
          (Net GND
            (Joined 
                (PortRef CLR (InstanceRef U1))
                (PortRef D0 (InstanceRef U1))
                (PortRef D1 (InstanceRef U1))
                (PortRef D2 (InstanceRef U1))
                (PortRef D3 (InstanceRef U1))
                (PortRef CLR (InstanceRef U8))
                (PortRef CLR (InstanceRef U9))
            )
          )
          (Net NetU1_C
            (Joined 
                (PortRef C (InstanceRef U1))
                (PortRef C (InstanceRef U8))
                (PortRef C (InstanceRef U9))
            )
          )
          (Net NetU1_CE
            (Joined 
                (PortRef CE (InstanceRef U1))
                (PortRef Q (InstanceRef U8))
            )
          )
          (Net NetU1_L
            (Joined 
                (PortRef L (InstanceRef U1))
            )
          )
          (Net NetU1_LEFT
            (Joined 
                (PortRef LEFT (InstanceRef U1))
                (PortRef Q (InstanceRef U9))
            )
          )
          (Net NetU1_SLI
            (Joined 
                (PortRef SLI (InstanceRef U1))
                (PortRef O (InstanceRef U3))
            )
          )
          (Net NetU1_SRI
            (Joined 
                (PortRef SRI (InstanceRef U1))
                (PortRef O (InstanceRef U4))
            )
          )
          (Net NetU2_I0
            (Joined 
                (PortRef I0 (InstanceRef U2))
                (PortRef I (InstanceRef U6))
            )
          )
          (Net NetU2_I1
            (Joined 
                (PortRef I1 (InstanceRef U2))
                (PortRef I (InstanceRef U7))
            )
          )
          (Net NetU2_O
            (Joined 
                (PortRef O (InstanceRef U2))
                (PortRef J (InstanceRef U8))
            )
          )
          (Net NetU5_I
            (Joined 
                (PortRef I (InstanceRef U5))
            )
          )
          (Net NetU5_O
            (Joined 
                (PortRef O (InstanceRef U5))
                (PortRef K (InstanceRef U8))
            )
          )
          (Net NetU6_O
            (Joined 
                (PortRef O (InstanceRef U6))
                (PortRef J (InstanceRef U9))
            )
          )
          (Net NetU7_O
            (Joined 
                (PortRef O (InstanceRef U7))
                (PortRef K (InstanceRef U9))
            )
          )
          (Net Q0
            (Joined 
                (PortRef Q0 (InstanceRef U1))
                (PortRef I (InstanceRef U4))
            )
          )
          (Net Q1
            (Joined 
                (PortRef Q1 (InstanceRef U1))
            )
          )
          (Net Q2
            (Joined 
                (PortRef Q2 (InstanceRef U1))
            )
          )
          (Net Q3
            (Joined 
                (PortRef Q3 (InstanceRef U1))
                (PortRef I (InstanceRef U3))
            )
          )
       )
     )
   )
  )
  (design Design_Counter_SchDoc
    (cellRef Counter_SchDoc
      (libraryRef SHEET_LIB)
    )
  )
)