mlt_arm_sitsang_rom.ldi

移植到WLIT项目的redboot源代码

// eCos memory layout - Tue Sep 05 18:46:49 2000

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>

MEMORY
{
    ram  : ORIGIN = 0xA0000000, LENGTH = 0x4000000
    rom  : ORIGIN = 0x00000000, LENGTH = 0x800000
}

SECTIONS
{
    SECTIONS_BEGIN
    SECTION_rom_vectors (ram, 0xA0000000, AT(0x00000000))   // vector page gets remapped from ROM to RAM
    SECTION_text (rom, 0x00002000, LMA_EQ_VMA)
    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixed_vectors (rom, 0x20, LMA_EQ_VMA)
    SECTION_data (ram, 0xA000A000, FOLLOWING (.gcc_except_table))
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
//    CYG_LABEL_DEFN(__pci_window) = 0xf00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
    SECTIONS_END
}