mlt_arm_sitsang_roma.ldi

移植到WLIT项目的redboot源代码

// eCos memory layout - Sun Jan 14 22:42:04 2001

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>

MEMORY
{
    vecs : ORIGIN = 0, LENGTH = 0x1000
    rom : ORIGIN = 0x40000, LENGTH = 0x7c0000
    ram : ORIGIN = 0xa0000000, LENGTH = 0x2000000
}

SECTIONS
{
    SECTIONS_BEGIN
    SECTION_fixed_vectors (vecs, 0x20, LMA_EQ_VMA)
    SECTION_rom_vectors (rom, 0x40000, LMA_EQ_VMA)
    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_data (ram, 0xa000a000, FOLLOWING (.gcc_except_table))
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    SECTIONS_END
}