cotulla_def.h

移植到WLIT项目的redboot源代码

#define DSADR4     (volatile unsigned long *)( 0x40000244 )          // DMA Source Address Register channel 4
#define DTADR4     (volatile unsigned long *)( 0x40000248 )          // DMA Target Address Register channel 4
#define DCMD4      (volatile unsigned long *)( 0x4000024C )          // DMA Command Address Register channel 4
#define DDADR5     (volatile unsigned long *)( 0x40000250 )          // DMA Descriptor Address Register channel 5
#define DSADR5     (volatile unsigned long *)( 0x40000254 )          // DMA Source Address Register channel 5
#define DTADR5     (volatile unsigned long *)( 0x40000258 )          // DMA Target Address Register channel 5
#define DCMD5      (volatile unsigned long *)( 0x4000025C )          // DMA Command Address Register channel 5
#define DDADR6     (volatile unsigned long *)( 0x40000260 )          // DMA Descriptor Address Register channel 6
#define DSADR6     (volatile unsigned long *)( 0x40000264 )          // DMA Source Address Register channel 6
#define DTADR6     (volatile unsigned long *)( 0x40000268 )          // DMA Target Address Register channel 6
#define DCMD6      (volatile unsigned long *)( 0x4000026C )          // DMA Command Address Register channel 6
#define DDADR7     (volatile unsigned long *)( 0x40000270 )          // DMA Descriptor Address Register channel 7
#define DSADR7     (volatile unsigned long *)( 0x40000274 )          // DMA Source Address Register channel 7
#define DTADR7     (volatile unsigned long *)( 0x40000278 )          // DMA Target Address Register channel 7
#define DCMD7      (volatile unsigned long *)( 0x4000027C )          // DMA Command Address Register channel 7
#define DDADR8     (volatile unsigned long *)( 0x40000280 )          // DMA Descriptor Address Register channel 8
#define DSADR8     (volatile unsigned long *)( 0x40000284 )          // DMA Source Address Register channel 8
#define DTADR8     (volatile unsigned long *)( 0x40000288 )          // DMA Target Address Register channel 8
#define DCMD8      (volatile unsigned long *)( 0x4000028C )          // DMA Command Address Register channel 8
#define DDADR9     (volatile unsigned long *)( 0x40000290 )          // DMA Descriptor Address Register channel 9
#define DSADR9     (volatile unsigned long *)( 0x40000294 )          // DMA Source Address Register channel 9
#define DTADR9     (volatile unsigned long *)( 0x40000298 )          // DMA Target Address Register channel 9
#define DCMD9      (volatile unsigned long *)( 0x4000029C )          // DMA Command Address Register channel 9
#define DDADR10    (volatile unsigned long *)( 0x400002a0 )          // DMA Descriptor Address Register channel 10
#define DSADR10    (volatile unsigned long *)( 0x400002a4 )          // DMA Source Address Register channel 10
#define DTADR10    (volatile unsigned long *)( 0x400002a8 )          // DMA Target Address Register channel 10
#define DCMD10     (volatile unsigned long *)( 0x400002aC )          // DMA Command Address Register channel 10
#define DDADR11    (volatile unsigned long *)( 0x400002b0 )          // DMA Descriptor Address Register channel 11
#define DSADR11    (volatile unsigned long *)( 0x400002b4 )          // DMA Source Address Register channel 11
#define DTADR11    (volatile unsigned long *)( 0x400002b8 )          // DMA Target Address Register channel 11
#define DCMD11     (volatile unsigned long *)( 0x400002bC )          // DMA Command Address Register channel 11
#define DDADR12    (volatile unsigned long *)( 0x400002c0 )          // DMA Descriptor Address Register channel 12
#define DSADR12    (volatile unsigned long *)( 0x400002c4 )          // DMA Source Address Register channel 12     
#define DTADR12    (volatile unsigned long *)( 0x400002c8 )          // DMA Target Address Register channel 12     
#define DCMD12     (volatile unsigned long *)( 0x400002cC )          // DMA Command Address Register channel 12     
#define DDADR13    (volatile unsigned long *)( 0x400002d0 )          // DMA Descriptor Address Register channel 13     
#define DSADR13    (volatile unsigned long *)( 0x400002d4 )          // DMA Source Address Register channel 13     
#define DTADR13    (volatile unsigned long *)( 0x400002d8 )          // DMA Target Address Register channel 13     
#define DCMD13     (volatile unsigned long *)( 0x400002dC )          // DMA Command Address Register channel 13     
#define DDADR14    (volatile unsigned long *)( 0x400002e0 )          // DMA Descriptor Address Register channel 14     
#define DSADR14    (volatile unsigned long *)( 0x400002e4 )          // DMA Source Address Register channel 14     
#define DTADR14    (volatile unsigned long *)( 0x400002e8 )          // DMA Target Address Register channel 14     
#define DCMD14     (volatile unsigned long *)( 0x400002eC )          // DMA Command Address Register channel 14     
#define DDADR15    (volatile unsigned long *)( 0x400002f0 )          // DMA Descriptor Address Register channel 15     
#define DSADR15    (volatile unsigned long *)( 0x400002f4 )          // DMA Source Address Register channel 15     
#define DTADR15    (volatile unsigned long *)( 0x400002f8 )          // DMA Target Address Register channel 15     
#define DCMD15     (volatile unsigned long *)( 0x400002fC )          // DMA Command Address Register channel 15     
//     Full Function UART        
#define FFRBR      (volatile unsigned long *)( 0x40100000 )          // Receive Buffer Register (read only)   
//#define FFRBR      (volatile unsigned long *)( 0x40200000 )   
#define FFTHR      (volatile unsigned long *)( 0x40100000 )          // Transmit Holding Register (write only)     
//#define FFTHR      (volatile unsigned long *)( 0x40200000 )
#define FFIER      (volatile unsigned long *)( 0x40100004 )          // Interrupt Enable Register (read/write)  
//#define FFIER      (volatile unsigned long *)( 0x40200004 )   
#define FFIIR      (volatile unsigned long *)( 0x40100008 )          // Interrupt ID Register (read only) 
//#define FFIIR      (volatile unsigned long *)( 0x40200008 )    
#define FFFCR      (volatile unsigned long *)( 0x40100008 )          // FIFO Control Register (write only)   
//#define FFFCR      (volatile unsigned long *)( 0x40200008 )  
#define FFLCR      (volatile unsigned long *)( 0x4010000C )          // Line Control Register (read/write) 
//#define FFLCR      (volatile unsigned long *)( 0x4020000C )     
#define FFMCR      (volatile unsigned long *)( 0x40100010 )          // Modem Control Register (read/write) 
//#define FFMCR      (volatile unsigned long *)( 0x40200010 )    
#define FFLSR      (volatile unsigned long *)( 0x40100014 )          // Line Status Register (read only)   
//#define FFLSR      (volatile unsigned long *)( 0x40200014 )  
#define FFMSR      (volatile unsigned long *)( 0x40100018 )          // Modem Status Register (read only)    
//#define FFMSR      (volatile unsigned long *)( 0x40200018 ) 
#define FFSPR      (volatile unsigned long *)( 0x4010001C )          // Scratch Pad Register (read/write)     
//#define FFSPR      (volatile unsigned long *)( 0x4020001C )
#define FFDLL      (volatile unsigned long *)( 0x40100000 )          // baud divisor lower byte (read/write)    
//#define FFDLL      (volatile unsigned long *)( 0x40200000 ) 
#define FFDLH      (volatile unsigned long *)( 0x40100004 )          // baud divisor higher byte (read/write) 
//#define FFDLH      (volatile unsigned long *)( 0x40200004 )    
#define FFISR      (volatile unsigned long *)( 0x40100020 )          // slow Infrared Select Register (read/write)  
//#define FFISR      (volatile unsigned long *)( 0x40200020 )   
//     Bluetooth UART        
#define BTRBR      (volatile unsigned long *)( 0x40200000 )          // Receive Buffer Register (read only)     
#define BTTHR      (volatile unsigned long *)( 0x40200000 )          // Transmit Holding Register (write only)     
#define BTIER      (volatile unsigned long *)( 0x40200004 )          // Interrupt Enable Register (read/write)
#define BTIIR      (volatile unsigned long *)( 0x40200008 )          // Interrupt ID Register (read only)
#define BTFCR      (volatile unsigned long *)( 0x40200008 )          // FIFO Control Register (write only)
#define BTLCR      (volatile unsigned long *)( 0x4020000C )          // Line Control Register (read/write)
#define BTMCR      (volatile unsigned long *)( 0x40200010 )          // Modem Control Register (read/write)
#define BTLSR      (volatile unsigned long *)( 0x40200014 )          // Line Status Register (read only)
#define BTMSR      (volatile unsigned long *)( 0x40200018 )          // Modem Status Register (read only)
#define BTSPR      (volatile unsigned long *)( 0x4020001C )          // Scratch Pad Register (read/write)
#define BTDLL      (volatile unsigned long *)( 0x40200000 )          // baud divisor lower byte (read/write)
#define BTDLH      (volatile unsigned long *)( 0x40200004 )          // baud divisor higher byte (read/write)
#define BTISR      (volatile unsigned long *)( 0x40200020 )          // slow Infrared Select Register (read/write)
//     Standard UART   
#define STRBR      (volatile unsigned long *)( 0x40700000 )          // Receive Buffer Register (read only)
#define STTHR      (volatile unsigned long *)( 0x40700000 )          // Transmit Holding Register (write only)
#define STIER      (volatile unsigned long *)( 0x40700004 )          // Interrupt Enable Register (read/write)
#define STIIR      (volatile unsigned long *)( 0x40700008 )          // Interrupt ID Register (read only)
#define STFCR      (volatile unsigned long *)( 0x40700008 )          // FIFO Control Register (write only)
#define STLCR      (volatile unsigned long *)( 0x4070000C )          // Line Control Register (read/write)
#define STMCR      (volatile unsigned long *)( 0x40700010 )          // Modem Control Register (read/write)
#define STLSR      (volatile unsigned long *)( 0x40700014 )          // Line Status Register (read only)
#define STMSR      (volatile unsigned long *)( 0x40700018 )          // Reserved
#define STSPR      (volatile unsigned long *)( 0x4070001C )          // Scratch Pad Register (read/write)
#define STDLL      (volatile unsigned long *)( 0x40700000 )          // baud divisor lower byte (read/write)
#define STDLH      (volatile unsigned long *)( 0x40700004 )          // baud divisor higher byte (read/write)
#define STISR      (volatile unsigned long *)( 0x40700020 )          // slow Infrared Select Register (read/write)
//     I2C   
#define IBMR       (volatile unsigned long *)( 0x40301680 )          // I2C Bus Monitor Register - IBMR
#define IDBR       (volatile unsigned long *)( 0x40301688 )          // I2C Data Buffer Register - IDBR
#define ICR        (volatile unsigned long *)( 0x40301690 )          // I2C Control Register - ICR
#define ISR        (volatile unsigned long *)( 0x40301698 )          // I2C Status Register - ISR
#define ISAR       (volatile unsigned long *)( 0x403016A0 )          // I2C Slave Address Register - ISAR
//#define ICCR       (volatile unsigned long *)( 0x403016A8 )          // I2C Clock Count Register - ICCR
//     I2S   
#define SACR0      (volatile unsigned long *)( 0x40400000 )          // Global Control Register
#define SACR1      (volatile unsigned long *)( 0x40400004 )          // Serial Audio I2S/MSB-Justified Control Register
// -     0x4040-0008 )          // Reserved
#define SASR0      (volatile unsigned long *)( 0x4040000C )          // Serial Audio I2S/MSB-Justified Interface and FIFO Status Register
// -     0x4040-0010 )          // Reserved
#define SAIMR      (volatile unsigned long *)( 0x40400014 )          // Serial Audio Interrupt Mask Register
#define SAICR      (volatile unsigned long *)( 0x40400018 )          // Serial Audio Interrupt Clear Register
//      0x4040-001C  
//     through   
// Reserved    0x4040-0058 -  
#define SAITR      (volatile unsigned long *)( 0x4040005C )          // Serial Audio Interrupt Test Register
#define SADIV      (volatile unsigned long *)( 0x40400060 )          // "Audio clock divider register. See section Section 12.3, 揝erial Audio Clocks and Sampling Frequencies