xscale_test.c

移植到WLIT项目的redboot源代码

			*OutboundDbReg |= OB_DBELL_INTC;		/* try to clear specific source */
			return (1);
		}

		break;

	case INTD:

		/* check to see if we are looking at the correct interrupt */
		if (!(*OutboundIstatReg & OB_STAT_INTD))
		{
		#if 0
			printf ("OISR Mismatch!\n");
			printf ("OISR = 0x%X\n", *OutboundIstatReg);
			printf ("**** PCI INTD Error ****\n\n");

			/* try to clear all sources */
			*OutboundDbReg = (OB_DBELL_INTA|OB_DBELL_INTB|OB_DBELL_INTC|OB_DBELL_INTD);
		#endif
			return (0);
		}
		else
		{
			printf ("PCI INTD generated/received\n\n");
			printf ("OISR OK!\n");
			printf ("OISR = 0x%X\n", *OutboundIstatReg);
			printf ("**** PCI INTD Success ****\n\n");
			*OutboundDbReg |= OB_DBELL_INTD;		/* try to clear specific source */
			return (1);
		}

		break;

	default:
		printf ("Unknown interrupt received\n");
		return (0);
		break;
	}
	return (1);		/* interrupt sharing support requirement */
}


/*******************************************************************************
*
* i960Rx_seek - look for i960Rx CPUs on the PCI Bus
*
* This function is used by the PCI interrupt test to find and print out
* all PCI location of a particular i960Rx processor on the PCI bus.  Thses include
* boards based on the RP, RD, RM, and RN processors.  The device ID of one of 
* these processors is the input to the function.
*
*/
static void i960Rx_seek (UINT32 adapter_device_id)
{
int dev_index = 0;
PCI_DEVICE_LOCATION dev_info;
static char *i960Rx_name;

	/* get the common name for the current Rx processor */
	switch (adapter_device_id)
	{
	case I80960RN_ATU:
		i960Rx_name = " i960RN  ";
		break;
	case I80960RM_ATU:
		i960Rx_name = " i960RM  ";
		break;
	case I80960RP_ATU:
		i960Rx_name = "i960RP/RD";
		break;
	case I80303_ATU:
	default:
		i960Rx_name = " i80303  ";
		break;
	} 

	while (Device_Seek (FALSE, VENDOR_INTEL,
							 adapter_device_id,
							 dev_index, &dev_info) == OK)
	{
		/* set up this entry into the device array */
		i960Rx_devices[num_rx_devices].device_id = adapter_device_id;
		i960Rx_devices[num_rx_devices].busno = dev_info.bus_number;
		i960Rx_devices[num_rx_devices].devno = dev_info.device_number;
		i960Rx_devices[num_rx_devices].funcno = dev_info.function_number;


		printf ("   %d        %s  %d       %d         %d\n",  
							num_rx_devices, i960Rx_name,
							i960Rx_devices[num_rx_devices].busno,
							i960Rx_devices[num_rx_devices].devno,
							i960Rx_devices[num_rx_devices].funcno);
	
		dev_index++;		/* increment number of current i960Rx devices found */
		num_rx_devices++;	/* increment total number of i960Rx devices found */
	}
}


/*********************************************************************************
*
* pci_int_test - tests PCI interrupts on IQ80310 PCI buses
*
* This test allows full testing of PCI interrupt routing to a particular
* slot on the PCI bus.  It runs in conjunction with a Cyclone i960Rx-based
* board plugged into the target slot.  A default interrupt handler is connected
* for all four PCI interrupt pins on the target board.  The test then waits for 
* the target board to trigger each interrupt using the i960Rx doorbell registers.
* The test passes if all four interrupts are recieved and properly handled by the
* IQ80310.
*
*/
void pci_int_test (void)
{
	PCI_DEVICE_LOCATION devloc;
	int indexChoice = 0;
	UINT32 long_data;
	UINT32 *OutboundImaskReg;
    int intline_INTA, intline_INTB, intline_INTC, intline_INTD;
	
	num_rx_devices = 0;	
	
	printf ("Scanning PCI Bus for all supported i960Rx ATU Devices.....\n\n");

	printf (" Index    Processor   Bus   Device   Function\n");
	printf (" -----    ---------   ---   ------   --------\n");



	i960Rx_seek (I80960RN_ATU);
	i960Rx_seek (I80960RM_ATU);
	i960Rx_seek (I80960RP_ATU);
	i960Rx_seek	(I80303_ATU);

	if (num_rx_devices == 0)
	{
		printf ("\n*** No i960Rx ATU Found on PCI Bus ***\n");
		return;
	}

	printf ("Enter index number to use for test : ");
	indexChoice = decIn();
	printf ("\n\n");

	if (indexChoice >= num_rx_devices)
	{
		printf ("Invalid index chosen, exiting\n");
		return;
	}

	devloc.bus_number = i960Rx_devices[indexChoice].busno;
	devloc.device_number = i960Rx_devices[indexChoice].devno;
	devloc.function_number = i960Rx_devices[indexChoice].funcno;

	
	sys_read_config_dword (devloc.bus_number,
						   devloc.device_number,
						   devloc.function_number,
						   REGION0_BASE_OFFSET,(UINT32*)&long_data);

	messagingUnitBase = long_data & 0xfffffff0;
	printf ("Messaging Unit PCI Base Address = 0x%X\n", messagingUnitBase);
	OutboundImaskReg = (UINT32 *)(messagingUnitBase + 0x34);

	/* Normally, we would just read the intline value from the configuration
	   space to determine where the interrupt is routed.  However, the i960Rx
	   only requested interrupt resources for one interrupt at a time... */

	/* compute interrupt routing values */
	if ((pci_to_xint(devloc.device_number, INTA, (int*)&intline_INTA)) ||
		(pci_to_xint(devloc.device_number, INTB, (int*)&intline_INTB)) ||
		(pci_to_xint(devloc.device_number, INTC, (int*)&intline_INTC)) ||
		(pci_to_xint(devloc.device_number, INTD, (int*)&intline_INTD)) == ERROR)
	{
		printf ("Error: Unable to connect PCI interrupts with IQ80310 interrupts\n");
		return;
	}

	printf ("i960Rx INTA pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTA));
	printf ("i960Rx INTB pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTB));
	printf ("i960Rx INTC pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTC));
	printf ("i960Rx INTD pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTD));


	/* Connect i960Rx PCI INTA Handler */
	if (pci_isr_connect (INTA, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTA) 
		== ERROR )
	{
		printf ("Error Connecting INTA interrupt handler\n");
		return;
	}
	printf ("INTA Service Routine installed...\n");

	/* enable PCI INTA */
	enable_external_interrupt(SINTA_INT_ID);

	/* Connect i960Rx PCI INTB Handler */
	if (pci_isr_connect (INTB, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTB) 
		== ERROR)
	{
		printf ("Error Connecting INTB interrupt handler\n");
		return;
	}
	printf ("INTB Service Routine installed...\n");
	
	/* enable PCI INTB */
	enable_external_interrupt(SINTB_INT_ID);

	/* Connect i960Rx PCI INTC Handler */
	if (pci_isr_connect (INTC, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTC) 
		== ERROR)
	{
		printf ("Error Connecting INTC interrupt handler\n");
		return;
	}
	printf ("INTC Service Routine installed...\n");

	/* enable PCI INTC */
	enable_external_interrupt(SINTC_INT_ID);

	/* Connect i960Rx PCI INTD Handler */
	if (pci_isr_connect (INTD, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTD) 
		== ERROR)
	{
		printf ("Error Connecting INTD interrupt handler\n");
		return;
	}
	printf ("INTD Service Routine installed...\n");

	/* enable PCI INTD */
	enable_external_interrupt(SINTD_INT_ID);

	/* make sure that the Outbound interrupts aren't masked */
	*OutboundImaskReg &= ~(OB_STAT_INTA | OB_STAT_INTB | OB_STAT_INTC | OB_STAT_INTD);

	/* let the ISR do the rest of the work... */
	printf ("Waiting for the PCI Interrupts to be received...\n\n");
	printf ("Hit <CR> when the test is complete\n\n\n");
	
	hexIn();

	return;
}


/*******************************************/
/*  Battery Backup SDRAM memory write test */
/*******************************************/
static void battery_test_write (void)
{																																					
	unsigned long start_addr = SDRAM_BATTERY_TEST_BASE;  /* Address to write to */

	/* Data to be written to address and read after the board has been powered off and powered back on */
	UINT32 junk = BATTERY_TEST_PATTERN;		

	*(volatile UINT32 *)start_addr = junk;

	printf("\nThe value '");
	hex32out(BATTERY_TEST_PATTERN);
	printf ("' is now written in DRAM at address $");
	hex32out(SDRAM_BATTERY_TEST_BASE);
	printf(".\n\nYou can now power the board off, wait 60 seconds and power it back on.");
	printf("\nThen come back in the battery test menu and select option 2 to check data from DRAM.\n");

	printf ("\nPress return to continue.\n");
	(void) hexIn();
}


/******************************************/
/*  Battery Backup SDRAM memory read test */
/******************************************/
static void battery_test_read (void)
{
	unsigned long start_addr = SDRAM_BATTERY_TEST_BASE;  /* Address to read from */
	UINT32 value_written = BATTERY_TEST_PATTERN;  /* Data that was written */
	UINT32 value_read;	

	value_read = *(volatile UINT32 *)start_addr;

	printf ("Value written at address $");
	hex32out(SDRAM_BATTERY_TEST_BASE);
	printf (": ");
	hex32out(BATTERY_TEST_PATTERN);
	printf ("\nValue read at address $");
	hex32out(SDRAM_BATTERY_TEST_BASE);
	printf("   : ");
	hex32out(value_read);

	if (value_read == value_written) printf ("\n\nThe battery test is a success !\n");
	else
	{
		printf ("\n\n****************************\n");
		printf ("* The battery test failed. *\n");
		printf ("****************************\n");
	}

  printf ("\nBattery test done.\n");
  printf ("Press return to continue.\n");
  (void) hexIn();
}


/*************************************/
/*  Battery Backup SDRAM memory menu */
/*************************************/
static void battery_test_menu (void)
{
	/* Test Menu Table */
	static MENU_ITEM batteryMenu[] =
	{
		{"Write data to SDRAM",			battery_test_write,		NULL},
		{"Check data from SDRAM",		battery_test_read,		NULL},
	};

	unsigned int num_menu_items =	(sizeof (batteryMenu) / sizeof (batteryMenu[0]));

/*  char menu_title[15] = "\n Battery Backup SDRAM memory test."; */
  char menu_title[36] = "\n Battery Backup SDRAM memory test.";

	printf ("\n*************************************************************************\n");
	printf ("* This test will enable you to perform a battery test in 4 steps:       *\n"); 
	printf ("*  1/  Select option 1 to write the value '");
	hex32out(BATTERY_TEST_PATTERN);
	printf ("' to DRAM at address *\n*      $");
	hex32out(SDRAM_BATTERY_TEST_BASE);
	printf (",                                                       *\n"); 
	printf ("*  2/  Power the board off and wait 60 seconds,                         *\n"); 
	printf ("*  3/  Power the board back on,                                         *\n"); 
	printf ("*  4/  Select option 2 to read at address $");
	hex32out(SDRAM_BATTERY_TEST_BASE);
	printf (" and compare the     *\n*      value to the value written '");
	hex32out(BATTERY_TEST_PATTERN); 
	printf ("'.                           *\n");
	printf ("*************************************************************************");

	menu (batteryMenu, num_menu_items, menu_title, MENU_OPT_NONE);
	printf ("\n");
}

/* 01/11/01 jwf */
/* Make the user select their host test platform type from a list of choices. */
/* If the user picks a Cyclone SB923 then modify the Outbound PCI Translate Register on the IQ80310 for the SB923 */
void select_host_test_system (void)
{
	char selection;

	printf("Select your Host test system\n\n");
	printf("Make a selection by typing a number.\n\n");
	printf("1 - Cyclone SB923\n");
	printf("2 - Personal Computer or other\n");

	do
	{
		selection = xgetchar();
	}
	while( (selection != '1') && (selection != '2') );

	if (selection == '1')
	{
			/* Modify the Outbound PCI Translate Register for a SB923, at address 0x1254 */
		*(volatile UINT32 *) POMWVR_ADDR = 0xa0000000;
	}
}


/* 02/09/01 jwf */
/* Read the 80200 Coyanosa ID register */
/* Use a base address equal to the fourth memory location from the last memory location */
/* in a 32MB SDRAM DIMM */
/* Store from coprocessor register 15 to memory. */
/* ARM register R0 is the address after the transfer */
void read_coyanosa_id_reg (void)
{

	__asm__ ("ldr r0, = 0xA1FFFFFC");

	__asm__ ("mrc p15, 0, r1, c0, c0, 0");

	__asm__ ("str r1, [r0], #0");

}


/* 02/09/01 jwf */
/*
*Display the following version information.
*1. Software version of Red Boot or Cygnus Cygmon Rom Monitor.
*2. Cpld version.  Located in the 0xFE840000 (Read)
*3. Board Revision. Located at 0xFE830000 (Read)
*4. 80200 ID data Located in CP15 Register 0
*5. 80312 Stepping Located at 0x00001008
*/
void version_info (void)
{
	char board_rev;

/* show revision information for operating system */
#if CYGNUS_CYGMON_OS
	extern void version(void); /* is defined in monitor.c */
	version();
#endif

#if REDHAT_REDBOOT_OS
	extern void do_version(int argc, char *argv[]);/* is defined in main.c */
	do_version(0,0);
#endif

	board_rev = board_revision();
	if ( board_rev >= BOARD_REV_E )
	{
			/* read Board revision register and adjust numeric revision to letter revision, 0x1 <--> A */	
		printf("\nBoard Revision = %c\n",(*BOARD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );
	}
	else
	{
			/* Board letter revision might be A or B or C or D */	
		printf("\nBoard Revision Unknown!\n");
	}

		/* read CPLD revision register and adjust numeric revision to letter revision, 0x1 <--> A */
	printf("CPLD Revision = %c\n",(*CPLD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );

		/* Read the 80200 Coyanosa ID register */
	read_coyanosa_id_reg();

	printf( "80200 Revision ID = 0x%x\n", ( *(volatile unsigned long *) COYANOSA_ID_BASE_ADDR) );
	
		/* read the 80312 Yavapai Revision ID register */
	printf( "80312 Revision ID = %d\n", (*(volatile unsigned char *) RIDR_ADDR) );

	printf ("\n\nStrike <CR> to exit this test.\n\n");
	
	hexIn();

}


/* 02/09/01 jwf */
/* Determine if the CPLD supports a Board Revision Register. */
/* If a Board Revision Register exists then return the board revision number read from a dedicated CPLD register at memory address 0xfe830000 */
/* Otherwise return a default board revision number. */
char board_revision ()
{
		/* represents the ring indicator bit logic level in UART2 */
	unsigned char ri_state;

		/* holds a board revision number */
	char board_rev;

		/* access UART2 MSR at memory address 0xfe810006 through the CYGMON serial port, J9 */
	ri_state = *( unsigned char * ) 0xfe810006;
	ri_state &= RI_MASK;

		/* RI# pin on UART2 is grounded */
		/* CPLD design supports a Board Revision Register implemention */
	if(ri_state == RI_MASK)
	{
			/* read Board Revision register and isolate LSN */
		board_rev = (*BOARD_REV_REG_ADDR & BOARD_REV_MASK);

			/* Board Rev is at E or higher */
		if (board_rev >= BOARD_REV_E)
		{
			return (board_rev);
		}
	}

		/* RI# pin on UART2 is pulled up to 3.3V. */
		/* Unknown Board Revision! */
		/* Unable to determine a board revision because the CPLD Board Revision Register */
		/* was never implemented for IQ80310 PCI-700 board REVs A,B,C, or D. */
		/* set a default board revision value of 0x2 <--> Rev B. */
	board_rev = 0x2;

		/* return a default value */
	return (board_rev);
}