iq80310.h

移植到WLIT项目的redboot源代码

/*** Yavapai Registers ***/

/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
#define VIDR_ADDR	0x00001000
#define DIDR_ADDR	0x00001002
#define PCR_ADDR	0x00001004
#define PSR_ADDR	0x00001006
#define RIDR_ADDR	0x00001008
#define CCR_ADDR	0x00001009
#define CLSR_ADDR	0x0000100C
#define PLTR_ADDR	0x0000100D
#define HTR_ADDR	0x0000100E
/* Reserved 0x0000100F through  0x00001017 */
#define PBNR_ADDR	0x00001018
#define SBNR_ADDR	0x00001019
#define SUBBNR_ADDR	0x0000101A
#define SLTR_ADDR	0x0000101B
#define IOBR_ADDR	0x0000101C
#define IOLR_ADDR	0x0000101D
#define SSR_ADDR	0x0000101E
#define MBR_ADDR	0x00001020
#define MLR_ADDR	0x00001022
#define PMBR_ADDR	0x00001024
#define PMLR_ADDR	0x00001026
/* Reserved 0x00001028 through 0x00001033 */
#define BSVIR_ADDR	0x00001034
#define BSIR_ADDR	0x00001036
/* Reserved 0x00001038 through 0x0000103D */
#define BCR_ADDR	0x0000103E
#define EBCR_ADDR	0x00001040
#define	SISR_ADDR	0x00001042
#define PBISR_ADDR	0x00001044
#define SBISR_ADDR	0x00001048
#define SACR_ADDR	0x0000104C
#define PIRSR_ADDR	0x00001050
#define SIOBR_ADDR	0x00001054
#define SIOLR_ADDR	0x00001055
#define SCCR_ADDR	0x00001056		/* EAS inconsistent */
#define SMBR_ADDR	0x00001058
#define SMLR_ADDR	0x0000105A
#define SDER_ADDR	0x0000105C
#define QCR_ADDR	0x0000105E
#define CDTR_ADDR	0x00001060		/* EAS inconsistent */
/* Reserved 0x00001064 through 0x000010FFH */

/* Performance Monitoring Unit 0000 1100H through 0000 11FFH */
#define GMTR_ADDR	0x00001100
#define ESR_ADDR	0x00001104
#define EMISR_ADDR	0x00001108
/* Reserved 0x0000110C */			/* EAS inconsistent */
#define GTSR_ADDR	0x00001110		/* EAS inconsistent */
#define PECR1_ADDR	0x00001114		/* EAS inconsistent */
#define PECR2_ADDR	0x00001118		/* EAS inconsistent */
#define PECR3_ADDR	0x0000111C		/* EAS inconsistent */
#define PECR4_ADDR	0x00001120		/* EAS inconsistent */
#define PECR5_ADDR	0x00001124		/* EAS inconsistent */
#define PECR6_ADDR	0x00001128		/* EAS inconsistent */
#define PECR7_ADDR	0x0000112C		/* EAS inconsistent */
#define PECR8_ADDR	0x00001130		/* EAS inconsistent */
#define PECR9_ADDR	0x00001134		/* EAS inconsistent */
#define PECR10_ADDR	0x00001138		/* EAS inconsistent */
#define PECR11_ADDR	0x0000113C		/* EAS inconsistent */
#define PECR12_ADDR	0x00001140		/* EAS inconsistent */
#define PECR13_ADDR	0x00001144		/* EAS inconsistent */
#define PECR14_ADDR	0x00001148		/* EAS inconsistent */
/* Reserved 0x0000104C through 0x000011FFH */	/* EAS inconsistent */

/* Address Translation Unit 0000 1200H through 0000 12FFH */
#define ATUVID_ADDR		0x00001200
#define ATUDID_ADDR		0x00001202
#define PATUCMD_ADDR	0x00001204
#define PATUSR_ADDR		0x00001206
#define ATURID_ADDR		0x00001208
#define ATUCCR_ADDR		0x00001209
#define ATUCLSR_ADDR	0x0000120C
#define ATULT_ADDR		0x0000120D
#define ATUHTR_ADDR		0x0000120E
#define ATUBISTR_ADDR	0x0000120F
#define PIABAR_ADDR		0x00001210
/* Reserved 0x00001214 through 0x0000122B */
#define ASVIR_ADDR		0x0000122C
#define ASIR_ADDR		0x0000122E
#define ERBAR_ADDR		0x00001230
/* Reserved 0x00001234 */
/* Reserved 0x00001238 */
#define ATUILR_ADDR		0x0000123C
#define ATUIPR_ADDR		0x0000123D
#define ATUMGNT_ADDR	0x0000123E
#define ATUMLAT_ADDR	0x0000123F
#define PIALR_ADDR		0x00001240
#define PIATVR_ADDR		0x00001244
#define SIABAR_ADDR		0x00001248
#define SIALR_ADDR		0x0000124C
#define SIATVR_ADDR		0x00001250
#define POMWVR_ADDR		0x00001254
/* Reserved 0x00001258 */
#define POIOWVR_ADDR	0x0000125C
#define PODWVR_ADDR		0x00001260
#define POUDR_ADDR		0x00001264
#define SOMWVR_ADDR		0x00001268
#define SOIOWVR_ADDR	0x0000126C
/* Reserved 0x00001270 */
#define ERLR_ADDR		0x00001274
#define ERTVR_ADDR		0x00001278
/* Reserved 0x0000127C */
/* Reserved 0x00001280 */
/* Reserved 0x00001284 */
#define ATUCR_ADDR		0x00001288
/* Reserved 0x0000128C */
#define PATUISR_ADDR	0x00001290
#define SATUISR_ADDR	0x00001294
#define SATUCMD_ADDR	0x00001298
#define SATUSR_ADDR		0x0000129A
#define SODWVR_ADDR		0x0000129C
#define SOUDR_ADDR		0x000012A0
#define POCCAR_ADDR		0x000012A4
#define SOCCAR_ADDR		0x000012A8
#define POCCDR_ADDR		0x000012AC
#define SOCCDR_ADDR		0x000012B0
#define PAQCR_ADDR		0x000012B4
#define SAQCR_ADDR		0x000012B8
#define PAIMR_ADDR		0x000012BC
#define SAIMR_ADDR		0x000012C0
/* Reserved 0x000012C4 through 0x000012FF */

/* Messaging Unit 0000 1300H through 0000 130FH */
#define IMR0_ADDR		0x00001310
#define IMR1_ADDR		0x00001314
#define OMR0_ADDR		0x00001318
#define OMR1_ADDR		0x0000131C
#define IDR_ADDR		0x00001320
#define IISR_ADDR		0x00001324
#define IIMR_ADDR		0x00001328
#define ODR_ADDR		0x0000132C
#define OISR_ADDR		0x00001330
#define OIMR_ADDR		0x00001334
/* Reserved 0x00001338 through 0x0000134F */
#define MUCR_ADDR		0x00001350
#define QBAR_ADDR		0x00001354
/* Reserved 0x00001358 */
/* Reserved 0x0000135C */
#define IFHPR_ADDR		0x00001360
#define IFTPR_ADDR		0x00001364
#define IPHPR_ADDR		0x00001368
#define IPTPR_ADDR		0x0000136C
#define OFHPR_ADDR		0x00001370
#define OFTPR_ADDR		0x00001374
#define OPHPR_ADDR		0x00001378
#define OPTPR_ADDR		0x0000137C
#define IAR_ADDR		0x00001380
/* Reserved 0x00001384 through 0x000013FF */

/* DMA Controller 0000 1400H through 0000 14FFH */
#define	CCR0_ADDR		0x00001400
#define CSR0_ADDR		0x00001404
/* Reserved 0x00001408 */
#define DAR0_ADDR		0x0000140C
#define NDAR0_ADDR		0x00001410
#define PADR0_ADDR		0x00001414
#define PUADR0_ADDR		0x00001418
#define LADR0_ADDR		0x0000141C
#define BCR0_ADDR		0x00001420
#define DCR0_ADDR		0x00001424
/* Reserved 0x00001428 through 0x0000143F */
#define CCR1_ADDR		0x00001440
#define CSR1_ADDR		0x00001444
/* Reserved 0x00001448 */
#define DAR1_ADDR		0x0000144C
#define NDAR1_ADDR		0x00001450
#define PADR1_ADDR		0x00001454
#define PUADR1_ADDR		0x00001458
#define LADR1_ADDR		0x0000145C
#define BCR1_ADDR		0x00001460
#define DCR1_ADDR		0x00001464
/* Reserved 0x00001468 through 0x0000147F */
#define CCR2_ADDR		0x00001480
#define CSR2_ADDR		0x00001484
/* Reserved 0x00001488 */
#define DAR2_ADDR		0x0000148C
#define NDAR2_ADDR		0x00001490
#define PADR2_ADDR		0x00001494
#define PUADR2_ADDR		0x00001498
#define LADR2_ADDR		0x0000149C
#define BCR2_ADDR		0x000014A0
#define DCR2_ADDR		0x000014A4
/* Reserved 0x000014A8 through 0x000014FF */

/* Memory Controller 0000 1500H through 0000 15FFH */
#define SDIR_ADDR		0x00001500
#define SDCR_ADDR		0x00001504
#define SDBR_ADDR		0x00001508
#define SBR0_ADDR		0x0000150C
#define SBR1_ADDR		0x00001510
#define SDPR0_ADDR		0x00001514
#define SDPR1_ADDR		0x00001518
#define SDPR2_ADDR		0x0000151C
#define SDPR3_ADDR		0x00001520
#define SDPR4_ADDR		0x00001524
#define SDPR5_ADDR		0x00001528
#define SDPR6_ADDR		0x0000152C
#define SDPR7_ADDR		0x00001530
#define ECCR_ADDR		0x00001534
#define ELOG0_ADDR		0x00001538
#define ELOG1_ADDR		0x0000153C
#define ECAR0_ADDR		0x00001540
#define ECAR1_ADDR		0x00001544
#define ECTST_ADDR		0x00001548
#define FEBR0_ADDR		0x0000154C
#define FEBR1_ADDR		0x00001550
#define FBSR0_ADDR		0x00001554
#define FBSR1_ADDR		0x00001558
#define FWSR0_ADDR		0x0000155C
#define FWSR1_ADDR		0x00001560
#define MCISR_ADDR		0x00001564
#define RFR_ADDR		0x00001568
/* Reserved 0x0000156C through 0x000015FF */

/* Arbitration Control Unit 0000 1600H through 0000 167FH */
#define IACR_ADDR		0x00001600
#define MLTR_ADDR		0x00001604
#define MTTR_ADDR		0x00001608
/* Reserved 0x0000160C through 0x0000163F */

/* Bus Interface Control Unit 0000 1640H through 0000 167FH */
#define BIUCR_ADDR		0x00001640
#define BIUISR_ADDR		0x00001644
/* Reserved 0x00001648 through 0x0000167F */

/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
#define ICR_ADDR		0x00001680
#define ISR_ADDR		0x00001684
#define ISAR_ADDR		0x00001688
#define IDBR_ADDR		0x0000168C
#define ICCR_ADDR		0x00001690
#define IBMR_ADDR		0x00001694
/* Reserved 0x00001698 through 0x000016FF */

/* PCI And Peripheral Interrupt Controller 0000 1700H through 0000 17FFH */
#define NISR_ADDR		0x00001700
#define X7ISR_ADDR		0x00001704
#define X6ISR_ADDR		0x00001708
#define PDIDR_ADDR		0x00001710		/* EAS inconsistent */
/* Reserved 0x00001714 through 0x0000177F */

/* Application Accelerator Unit 0000 1800H through 0000 18FFH */
#define ACR_ADDR		0x00001800
#define ASR_ADDR		0x00001804
#define ADAR_ADDR		0x00001808
#define ANDAR_ADDR		0x0000180C
#define SAR1_ADDR		0x00001810
#define SAR2_ADDR		0x00001814
#define SAR3_ADDR		0x00001818
#define SAR4_ADDR		0x0000181C
#define DAR_ADDR		0x00001820
#define ABCR_ADDR		0x00001824
#define ADCR_ADDR		0x00001828
#define SAR5_ADDR		0x0000182C
#define SAR6_ADDR		0x00001830
#define SAR7_ADDR		0x00001834
#define SAR8_ADDR		0x00001838

/* Reserved 0x0000183C through 0x000018FF */