interrupts.c

移植到WLIT项目的redboot源代码

			sint_status &= SINT_MASK;			/* isolate SINTA, SINTB, and SINTC */
			switch(sint_status)
			{
				case SINTA_INT:
					num_sources += sinta_handler();	/* IRQ0 = SINTA? */
/*					printf(" sinta status = %#x\n", sint_status); */
					break;
				case SINTB_INT:
					num_sources += sintb_handler();	/* IRQ1 = SINTB? */
/*					printf(" sintb status = %#x\n", sint_status); */
					break;			
				case SINTC_INT:
					num_sources += sintc_handler();	/* IRQ2 = SINTC? */
/*					printf(" sintc status = %#x\n", sint_status); */
					break;
				default:
/*					printf(" sint? status = %#x\n", sint_status); */
					break;						/* probably should test for more conditions: 011b, 101b, 110b, 111b */
			}
		}
	}
	else										/* RI# pin on UART2 is pulled up to 3.3V. Cannot read board revision register, not implemented */
	{
		num_sources += sinta_handler();			/* IRQ0 = SINTA? */
		num_sources += sintb_handler();			/* IRQ1 = SINTB? */
		num_sources += sintc_handler();			/* IRQ2 = SINTC? */
	}


	/* 12/18/00 jwf */
	/* Original code */
	/* No S_INTA - S_INTC status register, call handlers always */
	/* This may change in next revision of board */
	/*num_sources += sinta_handler();*/	/* IRQ0 = SINTA? */
	/*num_sources += sintb_handler();*/	/* IRQ1 = SINTB? */
	/*num_sources += sintc_handler();*/	/* IRQ2 = SINTC? */


	/* Read IRQ3 Status Register, and if any of the multiple sources are 
	   interrupting, call corresponding handler */
	int_status_reg = (UINT8 *)X3ISR_ADDR;
	int_status = *int_status_reg;
	{ 
		if (int_status & TIMER_INT) /* timer interrupt? */
		{
			/* call user ISR, if connected */
			if (usr_timer_isr != NULL)
				(*usr_timer_isr)(usr_timer_arg);
			else
				printf ("\nUnhandled Timer Interrupt Detected!\n");
			
			num_sources++;
		}

		if (int_status & ENET_INT)	/* ethernet interrupt? */
		{
			/* call user ISR, if connected */
			if (usr_enet_isr != NULL)
				(*usr_enet_isr)(usr_enet_arg);
			else
				printf ("\nUnhandled Ethernet Interrupt Detected!\n");

			num_sources++;
		}

		if (int_status & UART1_INT) /* uart1 interrupt? */
		{
			/* call user ISR, if connected */
			if (usr_uart1_isr != NULL)
				(*usr_uart1_isr)(usr_uart1_arg);
			else
				printf ("\nUnhandled UART1 Interrupt Detected!\n");

			num_sources++;
		}

		if (int_status & UART2_INT) /* uart2 interrupt? */
		{
			/* call user ISR, if connected */
			if (usr_uart2_isr != NULL)
				(*usr_uart2_isr)(usr_uart2_arg);
			else
				printf ("\nUnhandled UART2 Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & SINTD_INT)	/* SPCI_INTD? */
		{
			num_sources += sintd_handler();
		}
	}


	/* Read XINT6 Status Register, and if any of the multiple sources are 
	   interrupting, call corresponding handler */
	int_status_reg = (UINT8 *)X6ISR_ADDR;
	int_status = *int_status_reg;
	{
		if (int_status & DMA0_INT) /* dma0 interrupt? */
		{
			if (usr_dma0_isr != NULL)
				(*usr_dma0_isr)(usr_dma0_arg);
			else
				printf ("\nUnhandled DMA Channel 0 Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & DMA1_INT) /* dma1 interrupt? */
		{
			if (usr_dma1_isr != NULL)
				(*usr_dma1_isr)(usr_dma1_arg);
			else
				printf ("\nUnhandled DMA Channel 1 Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & DMA2_INT) /* dma2 interrupt? */
		{
			if (usr_dma2_isr != NULL)
				(*usr_dma2_isr)(usr_dma2_arg);
			else
				printf ("\nUnhandled DMA Channel 2 Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & PM_INT) /* performance monitoring interrupt? */
		{
			if (usr_pm_isr != NULL)
				(*usr_pm_isr)(usr_pm_arg);
			else
				printf ("\nUnhandled Performance Monitoring Unit Interrupt Detected!\n");
			num_sources++;
		}
		
		if (int_status & AA_INT) /* application accelerator interrupt? */
		{
			if (usr_aa_isr != NULL)
				(*usr_aa_isr)(usr_aa_arg);
			else
				printf ("\nUnhandled Application Accelerating Unit Interrupt Detected!\n");
			num_sources++;
		}
	}


	/* Read XINT7 Status Register, and if any of the multiple sources are 
	   interrupting, call corresponding handler */
	int_status_reg = (UINT8 *)X7ISR_ADDR;
	int_status = *int_status_reg;
	{
		if (int_status & I2C_INT) /* i2c interrupt? */
		{
			if (usr_i2c_isr != NULL)
				(*usr_i2c_isr)(usr_i2c_arg);
			else
				printf ("\nUnhandled I2C Unit Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & MU_INT) /* messaging unit interrupt? */
		{	
			if (usr_mu_isr != NULL)
				(*usr_mu_isr)(usr_mu_arg);
			else
				printf ("\nUnhandled Messaging Unit Interrupt Detected!\n");
			num_sources++;
		}

		if (int_status & PATU_INT) /* primary ATU / BIST start interrupt? */
		{
			if (usr_patu_isr != NULL)
				(*usr_patu_isr)(usr_patu_arg);
			else
				printf ("\nUnhandled Primary ATU Interrupt Detected!\n");
			num_sources++;
		}
	}

	/* return the number of interrupt sources found */
	return (num_sources);
}





/****************************************************************
*  nmi_ecc_isr - ECC NMI Interrupt Handler
*
*  This module handles the NMI caused by an ECC error.
*  For a Single-bit error it does a read-nodify-write
*  to correct the error in memory. For a multi-bit or
*  nibble error it does absolutely nothing.
*/
void nmi_ecc_isr(void)
{
	UINT32 eccr_register;
	UINT32* reg32;

	/* Read current state of ECC register */
	eccr_register = *(UINT32 *)ECCR_ADDR;

	/* Turn off all ecc error reporting */
	*(UINT32 *)ECCR_ADDR = 0x4;

	/* Check for ECC Error 0 */
	if(*(UINT32 *)MCISR_ADDR & 0x1)
	{
        reg32 = (UINT32*)ELOG0_ADDR;
		error_print("ELOG0 = 0x%X\n",*reg32,0,0,0);
		
		reg32 = (UINT32*)ECAR0_ADDR;
		error_print("ECC Error Detected at Address 0x%X\n",*reg32,0,0,0);		
	
		/* Check for single-bit error */
        if(!(*(UINT32 *)ELOG0_ADDR & 0x00000100))
        {
			/* call ECC restoration function */
			_scrub_ecc(*reg32);

			/* Clear the MCISR */
		    *(UINT32 *)MCISR_ADDR = 0x1;
        }
        else
            error_print("Multi-bit or nibble error\n",0,0,0,0);
	}

	/* Check for ECC Error 1 */
	if(*(UINT32 *)MCISR_ADDR & 0x2)
	{
		reg32 = (UINT32*)ELOG1_ADDR;
		error_print("ELOG0 = 0x%X\n",*reg32,0,0,0);
		
		reg32 = (UINT32*)ECAR1_ADDR;
		error_print("ECC Error Detected at Address 0x%X\n",*reg32,0,0,0);	
        
		/* Check for single-bit error */
        if(!(*(UINT32 *)ELOG1_ADDR & 0x00000100))
        {
			/* call ECC restoration function */
			_scrub_ecc(*reg32);
 
			/* Clear the MCISR */
			*(UINT32 *)MCISR_ADDR = 0x2;
       }
       else
            error_print("Multi-bit or nibble error\n",0,0,0,0);
	}

	/* Check for ECC Error N */
	if(*(UINT32 *)MCISR_ADDR & 0x4)
	{
		/* Clear the MCISR */
		*(UINT32 *)MCISR_ADDR = 0x4;
		error_print("Uncorrectable error during RMW\n",0,0,0,0);
	}
    
	/* Turn on  ecc error reporting */
	*(UINT32 *)ECCR_ADDR = eccr_register;
}




/******************************************************************************
* iq80310_fiq_handler - Interrupt dispatcher for IQ80310 FIQ Interrupts
*
*
*/
int iq80310_fiq_handler()
{
	
unsigned long nmi_status = *(volatile unsigned long *)NISR_ADDR;
unsigned long status;
int srcs_found = 0;

	if (nmi_status & MCU_ERROR)
	{
		status = *(volatile unsigned long *)MCISR_ADDR;
		*MSB_DISPLAY_REG = LETTER_E;
		if (status & 0x001)
			*LSB_DISPLAY_REG = ONE;
		if (status & 0x002)
			*LSB_DISPLAY_REG = TWO;
		if (status & 0x004)
			*LSB_DISPLAY_REG = FOUR;
		srcs_found++;
#if 0
		error_print ("**** 80312 Memory Controller Error ****\n",0,0,0,0);
		if (status & 0x001) error_print ("One ECC Error Detected and Recorded in ELOG0\n",0,0,0,0);
		if (status & 0x002) error_print ("Second ECC Error Detected and Recorded in ELOG1\n",0,0,0,0);
		if (status & 0x004) error_print ("Multiple ECC Errors Detected\n",0,0,0,0);
#endif

		/* call ecc interrupt handler */
		nmi_ecc_isr(); 

		/* clear the interrupt condition*/
		AND_WORD((volatile unsigned long *)MCISR_ADDR, 0x07);

/* 02/02/01 jwf */
		ecc_error_reported = TRUE;

	}


	if (nmi_status & PATU_ERROR)
	{
		srcs_found++;
		error_print ("**** Primary ATU Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)PATUISR_ADDR;
		if (status & 0x001) error_print ("PPCI Master Parity Error\n",0,0,0,0);
		if (status & 0x002) error_print ("PPCI Target Abort (target)\n",0,0,0,0);
		if (status & 0x004) error_print ("PPCI Target Abort (master)\n",0,0,0,0);
		if (status & 0x008) error_print ("PPCI Master Abort\n",0,0,0,0);
		if (status & 0x010) error_print ("Primary P_SERR# Detected\n",0,0,0,0);
		if (status & 0x080) error_print ("Internal Bus Master Abort\n",0,0,0,0);
		if (status & 0x100) error_print ("PATU BIST Interrupt\n",0,0,0,0);
		if (status & 0x200) error_print ("PPCI Parity Error Detected\n",0,0,0,0);
		if (status & 0x400) error_print ("Primary P_SERR# Asserted\n",0,0,0,0);

		/* clear the interrupt conditions */
		AND_WORD((volatile unsigned long *)PATUISR_ADDR, 0x79f);
		CLEAR_PATU_STATUS();

		/* tell the config cleanup code about error */
		if (pci_config_cycle == 1) 
			pci_config_error = TRUE;
	}

	if (nmi_status & SATU_ERROR)
	{
		srcs_found++;
		error_print ("**** Secondary ATU Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)SATUISR_ADDR;
		if (status & 0x001) error_print ("SPCI Master Parity Error\n",0,0,0,0);
		if (status & 0x002) error_print ("SPCI Target Abort (target)\n",0,0,0,0);
		if (status & 0x004) error_print ("SPCI Target Abort (master)\n",0,0,0,0);
		if (status & 0x008) error_print ("SPCI Master Abort\n",0,0,0,0);
		if (status & 0x010) error_print ("Secondary P_SERR# Detected\n",0,0,0,0);
		if (status & 0x080) error_print ("Internal Bus Master Abort\n",0,0,0,0);
		if (status & 0x200) error_print ("SPCI Parity Error Detected\n",0,0,0,0);
		if (status & 0x400) error_print ("Secondary S_SERR# Asserted\n",0,0,0,0);

		/* clear the interrupt conditions */
		AND_WORD((volatile unsigned long *)SATUISR_ADDR, 0x69f);
		CLEAR_SATU_STATUS();

		/* tell the config cleanup code about error */
		if (pci_config_cycle == 1) 
			pci_config_error = TRUE;
	}

	if (nmi_status & PBRIDGE_ERROR)
	{
		srcs_found++;
		error_print ("**** Primary Bridge Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)PBISR_ADDR;
		if (status & 0x001) error_print ("PPCI Master Parity Error\n",0,0,0,0);
		if (status & 0x002) error_print ("PPCI Target Abort (Target)\n",0,0,0,0);
		if (status & 0x004) error_print ("PPCI Target Abort (Master)\n",0,0,0,0);
		if (status & 0x008) error_print ("PPCI Master Abort\n",0,0,0,0);
		if (status & 0x010) error_print ("Primary P_SERR# Asserted\n",0,0,0,0);
		if (status & 0x020) error_print ("PPCI Parity Error Detected\n",0,0,0,0);

		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)PBISR_ADDR, 0x3f);
		CLEAR_PBRIDGE_STATUS();

		/* tell the config cleanup code about error */
		if (pci_config_cycle == 1) 
			pci_config_error = TRUE;
	}

	if (nmi_status & SBRIDGE_ERROR)
	{
		srcs_found++;