hal_platform_setup.h

移植到WLIT项目的redboot源代码

    2:
	ldr	r2, =BANKCNT_BYTE	// Check for bank count byte
	cmp	r6, r2
	bne	1f
	mov	r8, r1			// Store bank count
    1:
	ldr	r2, =BANKSZ_BYTE	// Check for bank size byte
	cmp	r6, r2
	bne	1f

	ldr	r2, =0x04		// Store bank size in Mbytes (shift left 2 bits)
	mul	r10, r1, r2
	mul	r2, r8, r10		// Multiply by bank count to get DRAM size in MB
	ldr	r0, =0x100000
	mul	r4, r2, r0		// Convert size to bytes  - r4 contains DRAM size in bytes

1:
	// Handle the SDRAM drive strength setup here since we are out of
	// temporary registers to hold the SDRAM width value until after
	// all of the SPD data has been read.  Using the value of r8 for
	// the Bank Count is allright here since the SPD specification states that
	// the Bank Count SPD byte is #5 and the SDRAM Width SPD byte is #13.

	ldr	r2, =SDRAM_WIDTH_BYTE 	// Check for SDRAM width byte
	cmp	r6, r2
	bne	1f
	mov	r2, #0x10	  // Check for data width of 16
	cmp	r1, r2
	bne	SDRAM_DRIVE_X8

	// Module is composed of x16 devices
	mov	r2, #0x02			
	cmp	r2, r8		// do we have 2 banks???
	beq	SDRAM_DRIVE_2_BANK_X16

	// Module is composed of 1 Bank of x16 devices
	ldr	r1, =SDCR_ADDR		// point at SDRAM Control Register
	ldr	r2, =SDCR_1BANK_X16	// drive strength value
	str	r2, [r1]		// set value in SDCR
	b	1f

SDRAM_DRIVE_2_BANK_X16:
	// Module is composed of 2 Banks of x16 devices
	ldr	r1, =SDCR_ADDR		// point at SDRAM Control Register
	ldr	r2, =SDCR_2BANK_X16	// drive strength value
	str	r2, [r1]		// set value in SDCR
	b	1f

SDRAM_DRIVE_X8:
	// Module is composed of x8 devices
	mov	r2, #0x02			
	cmp	r2, r8			// do we have 2 banks???
	beq	SDRAM_DRIVE_2_BANK_X8

	// Module is composed of 1 Bank of x8 devices
	ldr	r1, =SDCR_ADDR		// point at SDRAM Control Register
	ldr	r2, =SDCR_1BANK_X8	// drive strength value
	str	r2, [r1]		// set value in SDCR
	b	1f

SDRAM_DRIVE_2_BANK_X8:
	// Module is composed of 2 Banks of x16 devices
	ldr	r1, =SDCR_ADDR		// point at SDRAM Control Register
	ldr	r2, =SDCR_2BANK_X8	// drive strength value
	str	r2, [r1]		// set value in SDCR
    1:


	// Continue reading bytes if not done
	cmp	r6, r7
	bne	sdram_loop
	
	b	i2c_disable

    bad_checksum:
	HEX_DISPLAY r2, r3, DISPLAY_7, DISPLAY_7	

    i2c_error:
	// hit the leds if an error occurred
	HEX_DISPLAY r2, r3, DISPLAY_5, DISPLAY_5


    i2c_disable:
	//  Disable I2C Interface Unit
	ldr	r1, [r11] 
	bic	r1, r1, #ICR_ENB	// Disable I2C unit
	bic	r1, r1, #ICR_SCLENB	// Disable I2C clock generator
	str	r1, [r11]		// Store to control register
	
	// ADD THIS???:
	//  cmpobne	1, g9, test_init
	// Skip SDRAM controller initialization if checksum test failed

	// *** SDRAM setup ***

	ldr	r9, =MMR_BASE		// get base of MMRs
	ldr	r0, =RAM_BASE		// Program SDRAM Base Address register
	str	r0, [r9, #SDBR_OFF]    

	// Set up bank 0 register
    CHECK_32MB:
	ldr	r1, =RAM_32MEG		// do we have 32 MB banks?
	cmp	r10, r1
	bne	CHECK_64MB

	ldr	r0, =SBR_32MEG		// Program SDRAM Bank0 Boundary register to 32 MB
	b	SET_BANK1

    CHECK_64MB:
	ldr	r1, =RAM_64MEG		// do we have 64 MB banks?
	cmp	r10, r1
	bne	CHECK_128MB

	ldr	r0, =SBR_64MEG		// Program SDRAM Bank0 Boundary register to 64 MB
	b	SET_BANK1

    CHECK_128MB:
	ldr	r1, =RAM_128MEG		// do we have 128 MB banks?
	cmp	r10, r1
	bne	CHECK_256MB

	ldr	r0, =SBR_128MEG		// Program SDRAM Bank0 Boundary register to 128 MB
	b	SET_BANK1

    CHECK_256MB:
	ldr	r1, =RAM_256MEG		// do we have 256 MB banks?
	cmp	r10, r1
	bne	dram_error

	ldr	r0, =SBR_256MEG		// Program SDRAM Bank0 Boundary register to 64 MB
	b	SET_BANK1

    SET_BANK1:
	str	r0, [r9, #SBR0_OFF]	// store SBR0

	ldr	r2, =0x02			
	cmp	r2, r8			// do we have 2 banks???
	bne	SDRAM_1_BANK

	add	r0, r0, r0		// SDRAM Bank1 Boundary register is double SBR0
	str	r0, [r9, #SBR1_OFF]
	b	END_DRAM_SIZE

    SDRAM_1_BANK:
	// SDRAM Bank1 Boundary register is same as SBR0 for 1 bank configuration
	str	r0, [r9, #SBR1_OFF]
	b	END_DRAM_SIZE

    END_DRAM_SIZE:
	b	init_dram

    dram_error:

  	HEX_DISPLAY r2, r3, DISPLAY_F, DISPLAY_F

   init_dram:
	ldr	r0, =0			// turn off refresh
	str	r0, [r9, #RFR_OFF]
	
	ldr	r0,   =MRS_NO_OP        // Issue NOP cmd to SDRAM
	str	r0, [r9, #SDIR_OFF]
	DELAY_FOR 0x4000, r0
	
	ldr	r0, =MRS_PRECHRG	// Issue 1 Precharge all
	str	r0, [r9, #SDIR_OFF]    
	DELAY_FOR 0x4000, r0


	ldr	r0, =MRS_AUTO_RFRSH	// Issue 1 Auto Refresh command
	str	r0, [r9, #SDIR_OFF]    
	DELAY_FOR 0x4000, r0


	ldr	r0, =MRS_AUTO_RFRSH
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #1
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #2
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #3
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #4
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #5
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #6
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #7
	str	r0, [r9, #SDIR_OFF]    // Auto Refresh #8

	ldr	r0, =MRS_CAS_LAT_2	// set the CAS latency
	str	r0, [r9, #SDIR_OFF]
	DELAY_FOR 0x4000, r0
	
	ldr	r0, =MRS_NORM_OP	// Issue a Normal Operation command
	str	r0, [r9, #SDIR_OFF]     

	ldr	r0, =RFR_INIT_VAL	// Program Refresh Rate register
	str	r0, [r9, #RFR_OFF]     

	// ldr   r0, =(FLASH_BASE :AND: &FFFF0000)
	// str   r0, [r10, #FEBR1_OFF]   ; Program Flash Bank1 Base Address register

	// ldr   r0, =(FLASH_SIZE :AND: &FFFF0000)
	// str   r0, [r10, #FBSR1_OFF]   ; Program Flash Bank1 Size register

	// ldr   r0, =FWSR0_INIT_VAL
	// str   r0, [r10, #FWSR0_OFF]   ; Program Flash Bank0 Wait State register

	// ldr   r0, =FWSR1_INIT_VAL
	// str   r0, [r10, #FWSR1_OFF]   ; Program Flash Bank1 Wait State register

	HEX_DISPLAY r0, r1, DISPLAY_0, DISPLAY_2

	// begin initializing the i80310

	// Enable access to all coprocessor registers
	ldr	r0, =0x2001			// enable access to all coprocessors
	mcr	p15, 0, r0, c15, c1, 0
	
	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	mcr	p15, 0, r0, c7, c7, 0		// flush Icache, Dcache and BTB
	CPWAIT r0	
	
	mcr	p15, 0, r0, c8, c7, 0		// flush instuction and data TLBs
	CPWAIT r0	
	
	// Enable the Icache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_I
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	// Set the TTB register
	ldr	r0, =mmu_table
	mcr	p15, 0, r0, c2, c0, 0

	// Enable permission checks in all domains
	ldr	r0, =0x55555555
	mcr	p15, 0, r0, c3, c0, 0
	
	// Enable the MMU
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_M
	orr	r0, r0, #MMU_Control_R
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0
	
	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	// Enable the Dcache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_C
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	// Enable the BTB
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_BTB
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	//  Battery Backup SDRAM Memory Test
        //  Move 4 byte Test Pattern into register prior to zeroing out
	//  contents of SDRAM locations
	ldr	r9, =SDRAM_BATTERY_TEST_BASE
	ldr	r10, [r9]

	// scrub/init SDRAM if enabled/present
	ldr	r11, =RAM_BASE	// base address of SDRAM
	mov	r12, r4		// size of memory to scrub
	mov	r8,r4		// save DRAM size
	mov	r0, #0		// scrub with 0x0000:0000
	mov	r1, #0
	mov	r2, #0				
	mov	r3, #0
	mov	r4, #0					
	mov	r5, #0
	mov	r6, #0					
	mov	r7, #0
    10: // fastScrubLoop
	subs	r12, r12, #32	// 32 bytes/line
	stmia	r11!, {r0-r7}
	beq	15f
	b	10b
    15:	
	
	// Battery Backup SDRAM Memory Test
	// Store 4 byte Test Pattern back into memory
	str r10, [r9, #0x0]

	HEX_DISPLAY r0, r1, DISPLAY_1, DISPLAY_0

	// clean/drain/flush the main Dcache
	mov	r1, #DCACHE_FLUSH_AREA           // use a CACHEABLE area of
	                                         // the memory map above SDRAM
	mov	r0, #1024			 // number of lines in the Dcache
    20:
	mcr	p15, 0, r1, c7, c2, 5		 // allocate a Dcache line
	add	r1, r1, #32			 // increment the address to
	                                         // the next cache line
	subs	r0, r0, #1			 // decrement the loop count
	bne	20b

	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_9

	// clean/drain/flush the mini Dcache
	ldr	r2, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
	                                        // the memory map above SDRAM
	mov	r0, #64			        // number of lines in the mini Dcache
    21:
	mcr	p15, 0, r2, c7, c2, 5		// allocate a Dcache line
	add	r2, r2, #32			// increment the address to
  	                                        // the next cache line
	subs	r0, r0, #1			// decrement the loop count
	bne	21b

	mcr	p15, 0, r0, c7, c6, 0		// flush Dcache
	CPWAIT r0
	
	HEX_DISPLAY r0, r1, DISPLAY_7, DISPLAY_7

	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	// enable ECC stuff here
	mcr p15, 0, r0, c7, c10, 4		// 
	CPWAIT r0

	mrc	p13, 0, r0, c0, c1, 0		// BCU_WAIT --> wait until the BCU isn't busy
	submi	pc, pc, #0xc
	
    checkme:	// add in multi-bit error reporting */
	mrc	p13, 0, r0, c0, c1, 0		// disable ECC
	and	r0, r0, #(-1-8)
	mcr	p13, 0, r0, c0, c1, 0		
	orr	r0, r0, #6			// enable single-bit correction,
	mcr	p13, 0, r0, c0, c1, 0		// multi-bit detection
	orr	r0, r0, #8			// enable ECC
	mcr	p13, 0, r0, c0, c1, 0		

	mrc	p13, 0, r0, c0, c1, 0		// BCU_WAIT --> wait until the BCU isn't busy
	submi	pc, pc, #0xc

	// Enable ECC circuitry in Yavapai
	ldr	r1, =ECCR_ADDR
	mov	r0, #0x6  // Enable single bit ECC Correction (Reporting Enabled)
	str	r0, [r1, #0]

	HEX_DISPLAY r0, r1, DISPLAY_6, DISPLAY_6

#if 1
	mov	r0, #0x1000000
    1:  subs	r0,r0,#1
	bne	1b
#endif
	// Save SDRAM size
        ldr     r1, =hal_dram_size  /* [see hal_intr.h] */
	str	r8, [r1]

	// Move mmu tables into RAM so page table walks by the cpu
	// don't interfere with FLASH programming.
	ldr	r0, =mmu_table
	mov     r4, r0
	add     r2, r0, #0x4800     	// End of tables
	mov	r1, #RAM_BASE
	orr	r1, r1, #0x4000		// RAM tables
	mov     r5, r1

	// first, fixup physical address to second level
	// table used to map first 1MB of flash.
	ldr	r3, [r0], #4
	sub     r3, r3, r4
	add	r3, r3, r5
	str	r3, [r1], #4
	// everything else can go as-is
    1:
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	cmp	r0, r2
	bne	1b

	// go back and fixup physical address to second level
	// table used to map first 1MB of SDRAM.
	add     r1, r5, #(0xA00 * 4)
	ldr	r0, [r1]    		// entry for first 1MB of DRAM
	sub     r0, r0, r4
	add	r0, r0, r5
	str	r0, [r1]    		// store it back
	
	// Flush the cache
        mov    r0, #DCACHE_FLUSH_AREA	/* cache flush region */
        add    r1, r0, #0x8000		/* 32KB cache         */
  667:
        mcr    p15,0,r0,c7,c2,5		/* allocate a line    */
        add    r0, r0, #32       	/* 32 bytes/line      */
        teq    r1, r0
        bne    667b
        mcr    p15,0,r0,c7,c6,0		/* invalidate data cache */
        /* cpuwait */
        mrc    p15,0,r1,c2,c0,0		/* arbitrary read   */
        mov    r1,r1
        sub    pc,pc,#4
        mcr    p15,0,r0,c7,c10,4
        /* cpuwait */
        mrc    p15,0,r1,c2,c0,0		/* arbitrary read   */
        mov    r1,r1
        sub    pc,pc,#4
        nop

	HEX_DISPLAY r0, r1, DISPLAY_5, DISPLAY_2

	// Set the TTB register to DRAM mmu_table
	mov	r0, r5
	mov	r1, #0
	mcr	p15, 0, r1, c7, c5, 0		// flush I cache
	mcr	p15, 0, r1, c7, c10, 4		// drain WB
	mcr	p15, 0, r0, c2, c0, 0		// load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		// flush TLBs
	CPWAIT  r0

	// Interrupt init
        mov	r0, #0 // enable no sources
        mcr	p13,0,r0,c0,c0,0 // write to INTCTL
        // Steer both BCU and PMU to IRQ
        mcr	p13,0,r0,c8,c0,0 // write to INTSTR

	mov	r0,#0
	mcr	p15,0,r0,c14,c8,0  // ibcr0
	mcr	p15,0,r0,c14,c9,0  // ibcr1
	mcr	p15,0,r0,c14,c4,0  // dbcon
	mov	r0,#0x80000000
	mcr	p14,0,r0,c10,c0,0  // dcsr

	HEX_DISPLAY r0, r1, DISPLAY_0, DISPLAY_0

	.endm    // _platform_setup1


#define PLATFORM_VECTORS         _platform_vectors
        .macro  _platform_vectors
        .globl  _80312_EMISR
_80312_EMISR:   .long   0       // Companion chip "clear-on-read" interrupt status
				// register for the performance monitor unit.
        .endm                                        

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */